Feature - Product/Quotient/Remainder (PQR) Instruction Class

[Lichtso]

Multiplications and divisions will get a new more uniform and versatile instruction encoding in SBPFv2.

Scheme of the instruction encoding:

bit index	when 0	when 1
3	immediate	register
4	32 bit	64 bit
5	low product / quotient	high product / remainder
6	multiplication	division
7	unsigned	signed

Instructions of the new BPF_PQR class:

opcode (hex / bin)	BPF name	Assembler Mnemonic	deprecated SBPFv1
06 / 00000110	-- reserved --	-- reserved --
0E / 00001110	-- reserved --	-- reserved --
16 / 00010110	-- reserved --	-- reserved --
1E / 00011110	-- reserved --	-- reserved --
26 / 00100110	-- reserved --	-- reserved --
2E / 00101110	-- reserved --	-- reserved --
36 / 00110110	BPF_UHMUL64_IMM	uhmul64 dst, imm
3E / 00111110	BPF_UHMUL64_REG	uhmul64 dst, src
46 / 01000110	BPF_UDIV32_IMM	udiv32 dst, imm	34 / BPF_DIV32_IMM / div32 dst, imm
4E / 01001110	BPF_UDIV32_REG	udiv32 dst, src	3C / BPF_DIV32_REG / div32 dst, src
56 / 01010110	BPF_UDIV64_IMM	udiv64 dst, imm	37 / BPF_DIV64_IMM / div64 dst, imm
5E / 01011110	BPF_UDIV64_REG	udiv64 dst, src	3F / BPF_DIV64_REG / div64 dst, src
66 / 01100110	BPF_UREM32_IMM	urem32 dst, imm	94 / BPF_MOD32_IMM / mod32 dst, imm
6E / 01101110	BPF_UREM32_REG	urem32 dst, src	9C / BPF_MOD32_REG / mod32 dst, src
76 / 01110110	BPF_UREM64_IMM	urem64 dst, imm	97 / BPF_MOD64_IMM / mod64 dst, imm
7E / 01111110	BPF_UREM64_REG	urem64 dst, src	9F / BPF_MOD64_REG / mod64 dst, src
86 / 10000110	BPF_LMUL32_IMM	lmul32 dst, imm	24 / BPF_MUL32_IMM / mul32 dst, imm
8E / 10001110	BPF_LMUL32_REG	lmul32 dst, src	2C / BPF_MUL32_REG / mul32 dst, src
96 / 10010110	BPF_LMUL64_IMM	lmul64 dst, imm	27 / BPF_MUL64_IMM / mul64 dst, imm
9E / 10011110	BPF_LMUL64_REG	lmul64 dst, src	2F / BPF_MUL64_REG / mul64 dst, src
A6 / 10100110	-- reserved --	-- reserved --
AE / 10101110	-- reserved --	-- reserved --
B6 / 10110110	BPF_SHMUL64_IMM	shmul64 dst, imm
BE / 10111110	BPF_SHMUL64_REG	shmul64 dst, src
C6 / 11000110	BPF_SDIV32_IMM	sdiv32 dst, imm
CE / 11001110	BPF_SDIV32_REG	sdiv32 dst, src
D6 / 11010110	BPF_SDIV64_IMM	sdiv64 dst, imm
DE / 11011110	BPF_SDIV64_REG	sdiv64 dst, src
E6 / 11100110	BPF_SREM32_IMM	srem32 dst, imm
EE / 11101110	BPF_SREM32_REG	srem32 dst, src
F6 / 11110110	BPF_SREM64_IMM	srem64 dst, imm
FE / 11111110	BPF_SREM64_REG	srem64 dst, src

---

In the LLVM backend, the instruction info needs to be adjusted here:
https://github.com/solana-labs/llvm-project/blob/7b8db05b564faffb522434b73b7082662171f94a/llvm/lib/Target/SBF/SBFInstrInfo.td#L311

[codecov-commenter]

Codecov Report

Merging #498 (de1e7bf) into main (0c64b48) will decrease coverage by 0.26%.
Report is 1 commits behind head on main.
The diff coverage is 81.70%.

@@            Coverage Diff             @@
##             main     #498      +/-   ##
==========================================
- Coverage   89.55%   89.30%   -0.26%     
==========================================
  Files          23       23              
  Lines       10119    10283     +164     
==========================================
+ Hits         9062     9183     +121     
- Misses       1057     1100      +43     

Files Changed	Coverage Δ
src/disassembler.rs	84.72% <0.00%> (-8.65%)	⬇️
src/ebpf.rs	79.59% <ø> (ø)
src/interpreter.rs	92.59% <79.48%> (-5.09%)	⬇️
src/jit.rs	91.60% <86.20%> (-0.14%)	⬇️
src/assembler.rs	99.08% <100.00%> (+0.26%)	⬆️
src/elf.rs	87.41% <100.00%> (ø)
src/verifier.rs	97.69% <100.00%> (+0.19%)	⬆️

[dmakarov]

We don't use the original BPF backend of LLVM, since we have a separate SBF backend https://github.com/solana-labs/llvm-project/tree/7b8db05b564faffb522434b73b7082662171f94a/llvm/lib/Target/SBF

[Lichtso]

There is still an ongoing discussion about if we want to keep sign extension: solana-labs/solana#32924

And we are still missing a test for all the deprecated features. But that will go into another PR.