This repository implements on-device training and inference of a pre-defined sparse multi-layer perceptron neural network on an FPGA board -- as per research done by the USC HAL team.
This research paper has more details. Please consider citing it if you use or benefit from this work:
Sourya Dey, Diandian Chen, Zongyang Li, Souvik Kundu, Kuan-Wen Huang, Keith M. Chugg, Peter A. Beerel, "A Highly Parallel FPGA Implementation of Sparse Neural Network Training" in International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2018, pp. 1-4.
Available as a short paper on IEEE and full version on arXiv.
(Additional contributors who are not authors of the paper: Yinan Shao, Nishanth Narisetty, Mahdi Jelodari Mamaghani)
Main folder: DNN_MNIST_withUART
Tested and run using Xilinx Vivado.
Complete (and extremely specific) documentation is available here. This refers to the original repository internal to USC HAL (please contact Sourya Dey for access). This repository is a simplified version of the original.