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* 4.77Mhz CPU clock with 33% duty cycle, thanks to @MicroCoreLabs * Peripheral clock now works at half cpu clock, for correct synchronisation with the 8253 timer, thanks to @kitune-san * Turbo option is disabled for the moment, requires a redesign of the BIU... for the to-do list
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Original file line number | Diff line number | Diff line change |
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@@ -1,20 +1,31 @@ | ||
module clk_div3(clk, clk_out); | ||
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input clk; | ||
output clk_out; | ||
output reg clk_out; | ||
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reg [1:0] pos_count = 2'b00; | ||
reg [1:0] neg_count = 2'b00; | ||
wire [1:0] r_nxt; | ||
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always @(posedge clk) | ||
if (pos_count ==2) pos_count <= 0; | ||
else pos_count<= pos_count +1; | ||
//always @(posedge clk) | ||
//if (pos_count ==2) pos_count <= 0; | ||
//else pos_count<= pos_count +1; | ||
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always @(negedge clk) | ||
if (neg_count ==2) neg_count <= 0; | ||
else neg_count<= neg_count +1; | ||
//always @(negedge clk) | ||
//if (neg_count ==2) neg_count <= 0; | ||
//else neg_count<= neg_count +1; | ||
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assign clk_out = ((pos_count == 2) | (neg_count == 2)); | ||
//assign clk_out = ((pos_count == 2) | (neg_count == 2)); | ||
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endmodule | ||
always @(posedge clk) begin | ||
if (pos_count ==2) begin | ||
pos_count <= 0; | ||
clk_out <= 1'b1; | ||
end | ||
else begin | ||
pos_count<= pos_count +1; | ||
clk_out <= 1'b0; | ||
end | ||
end | ||
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endmodule |
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