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Beta 0.5
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* Added UART module from ao486 project (COM1 assigned to USER I/O pins)
* Automatic loading of the BIOS ROM from /games/PCXT directory
* BIOS ROM hot swapping from the OSD menu
* Updated the code to the latest version of the SDRAM module of KFPC-XT, but not yet implemented in the core... needs to be revised and improved, it does not work properly.
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@spark2k06
spark2k06 committed Jun 3, 2022
1 parent 6bd254e commit 2b56813
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Showing 41 changed files with 3,849 additions and 137 deletions.
22 changes: 21 additions & 1 deletion PCXT.qsf
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Expand Up @@ -290,6 +290,27 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_global_assignment -name VERILOG_FILE rtl/uart/uart.v
set_global_assignment -name QIP_FILE rtl/uart/uart.qip
set_global_assignment -name VHDL_FILE rtl/uart/gh_uart_Tx_8bit.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_uart_Rx_8bit.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_uart_16550.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_shift_reg_se_sl.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_shift_reg_PL_sl.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_register_ce.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_parity_gen_Serial.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_jkff.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_gray2binary.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_fifo_async16_rcsr_wf.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_fifo_async_sr.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_edge_det_XCD.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_edge_det.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_DECODE_3to8.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_counter_integer_down.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_counter_down_ce_ld_tc.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_counter_down_ce_ld.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_binary2gray.vhd
set_global_assignment -name VHDL_FILE rtl/uart/gh_baud_rate_gen.vhd
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_top.vhd
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_tone.vhd
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_noise.vhd
Expand Down Expand Up @@ -328,7 +349,6 @@ set_global_assignment -name VERILOG_FILE rtl/jtopl/hdl/jtopl_csr.v
set_global_assignment -name VERILOG_FILE rtl/jtopl/hdl/jtopl_acc.v
set_global_assignment -name VERILOG_FILE rtl/jtopl/hdl/jtopl.v
set_global_assignment -name QIP_FILE rtl/jtopl/hdl/jt26.qip
set_global_assignment -name VERILOG_FILE rtl/common/dpr.v
set_global_assignment -name VERILOG_FILE rtl/video/vram.v
set_global_assignment -name VERILOG_FILE rtl/video/crtc6845.v
set_global_assignment -name VERILOG_FILE rtl/video/cga_vram.v
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69 changes: 60 additions & 9 deletions PCXT.sv
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Expand Up @@ -173,11 +173,12 @@ module emu
///////// Default values for ports not used in this core /////////

assign ADC_BUS = 'Z;
assign USER_OUT = '1;
//assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
//assign SDRAM_CLK = CLK_50M;
//assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;

assign VGA_SL = 0;
assign VGA_F1 = 0;
Expand Down Expand Up @@ -258,10 +259,11 @@ wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_data;

wire clk_uart;

wire [21:0] gamma_bus;
wire adlibhide = status[10];

// PS2DIV : la mitad del divisor que necesitas para dividir el clk_sys que le das al hpio, para que te de entre 10Khz y 16Kzh
hps_io #(.CONF_STR(CONF_STR), .PS2DIV(2000), .PS2WE(1)) hps_io
(
.clk_sys(CLK_50M),
Expand Down Expand Up @@ -326,10 +328,15 @@ pll pll
.outclk_0(clk_100),
.outclk_1(clk_28_636),
.outclk_2(cen_opl2),
.outclk_3(clk_uart),
.locked(pll_locked)
);

//wire reset = RESET | status[0] | buttons[1];
<<<<<<< Updated upstream
=======
//wire reset = RESET | status[0] | buttons[1] | !pll_locked | (status[14] && usdImgMtd) | (ioctl_download && ioctl_index == 0);
>>>>>>> Stashed changes
wire reset = RESET | status[0] | buttons[1] | !pll_locked | (status[14] && usdImgMtd);

//////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -461,6 +468,7 @@ clk_div3 clk_normal // 4.77MHz

CHIPSET u_CHIPSET (
.clock (clk_cpu),
.clk_sys (CLK_50M),
.peripheral_clock (clk_4_77),

.reset (reset || splashscreen),
Expand Down Expand Up @@ -513,8 +521,27 @@ clk_div3 clk_normal // 4.77MHz
.clk_en_opl2 (cen_opl2), // clk_en_opl2
.jtopl2_snd_e (jtopl2_snd_e),
.adlibhide (adlibhide),
<<<<<<< Updated upstream
.tandy_snd_e (tandy_snd_e)

=======
.tandy_snd_e (tandy_snd_e),
.ioctl_download (ioctl_download),
.ioctl_index (ioctl_index),
.ioctl_wr (ioctl_wr),
.ioctl_addr (ioctl_addr),
.ioctl_data (ioctl_data),

.clk_uart (clk_uart),
.uart_rx (uart_rx),
.uart_tx (uart_tx),
.uart_cts_n (uart_cts),
.uart_dcd_n (uart_dcd),
.uart_dsr_n (uart_dsr),
.uart_rts_n (uart_rts),
.uart_dtr_n (uart_dtr)

>>>>>>> Stashed changes
);

wire [15:0] jtopl2_snd_e;
Expand All @@ -540,13 +567,37 @@ clk_div3 clk_normal // 4.77MHz
.s2_s0_out(processor_status),
.SEGMENT(SEGMENT)
);

/// UART


assign USER_OUT = {1'b1, 1'b1, uart_dtr, 1'b1, uart_rts, uart_tx, 1'b1};

//
// Pin | USB Name | |Signal
// ----+----------+---+-------------
// 0 | D+ | I |RX
// 1 | D- | O |TX
// 2 | TX- | O |RTS
// 3 | GND_d | I |CTS
// 4 | RX+ | O |DTR
// 5 | RX- | I |DSR
// 6 | TX+ | I |DCD
//

wire uart_tx, uart_rts, uart_dtr;

wire uart_rx = USER_IN[0];
wire uart_cts = USER_IN[3];
wire uart_dsr = USER_IN[5];
wire uart_dcd = USER_IN[6];

always @(posedge clk_cpu) begin
if (address_latch_enable)
cpu_address <= cpu_ad_out;
else
cpu_address <= cpu_address;
end
always @(posedge clk_cpu) begin
if (address_latch_enable)
cpu_address <= cpu_ad_out;
else
cpu_address <= cpu_address;
end

/*
wire [1:0] scale = status[8:7];
Expand Down
44 changes: 39 additions & 5 deletions SW/8088_bios/bios.asm
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Expand Up @@ -1278,11 +1278,45 @@ msg_iochk_nmi:
; Prints an error message since we don't have ROM BASIC
;-------------------------------------------------------------------------
int_18:
mov si,msg_no_basic
call print
.1:
hlt
jmp .1
;mov si,msg_no_basic
;call print
push ds
mov ax, 0f000h
mov ds, ax
mov ax, [0]
xchg al, ah
pop ds
call print_hex
push ds
mov ax, 0d000h
mov ds, ax
mov ax, [0]
xchg al, ah
pop ds
call print_hex
push ds
mov ax, 0e000h
mov ds, ax
mov ax, [0]
xchg al, ah
pop ds
call print_hex
mov ax, 0e375h
mov ss, ax
mov sp, 100h
xor ax, ax
mov es, ax
es mov word [84h], 98h
es mov word [86h], 0d000h
db 0eah,
dw 100h, 0d000h

;.1:
; hlt
; jmp .1

;=========================================================================
; int_19 - load and execute the boot sector
Expand Down
0 SW/bios-sergey-xt-xtide.bin → SW/boot.rom
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File renamed without changes.
12 changes: 0 additions & 12 deletions SW/make_boot0.py
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This file was deleted.

50 changes: 0 additions & 50 deletions SW/make_boot0_with_ibmbasic.py
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This file was deleted.

2 changes: 1 addition & 1 deletion SW/splash.txt
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Expand Up @@ -5,7 +5,7 @@
(_()((_|(_|_)) (_(_())/((_|()\ (_)) )\_____((_)(_(_())
| \/ |(_) __||_ _(_)) ((_) | _ ((/ __\ \/ /|_ _|
| |\/| || \__ \ | | / -_)| '_| | _/| (__ > < | |
|_| |_||_|___/ |_| \___||_| |_| \___/_/\_\ |_| 29/05/2022
|_| |_||_|___/ |_| \___||_| |_| \___/_/\_\ |_| 03/06/2022


Port by @spark2k06, @naeloob
Expand Down
Binary file added releases/PCXT_20220603.rbf
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Binary file not shown.
38 changes: 38 additions & 0 deletions rtl/KFPC-XT/HDL/Chipset.sv
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Expand Up @@ -4,6 +4,7 @@
//
module CHIPSET (
input logic clock,
input logic clk_sys,
input logic peripheral_clock,
input logic reset,
// CPU
Expand Down Expand Up @@ -70,7 +71,26 @@ module CHIPSET (
output logic [15:0] jtopl2_snd_e,
input logic adlibhide,
// TANDY SND
<<<<<<< Updated upstream
output logic [7:0] tandy_snd_e,
=======
output logic [7:0] tandy_snd_e,
// IOCTL
input logic ioctl_download,
input logic [7:0] ioctl_index,
input logic ioctl_wr,
input logic [24:0] ioctl_addr,
input logic [7:0] ioctl_data,
// UART
input logic clk_uart,
input logic uart_rx,
output logic uart_tx,
input logic uart_cts_n,
input logic uart_dcd_n,
input logic uart_dsr_n,
output logic uart_rts_n,
output logic uart_dtr_n,
>>>>>>> Stashed changes
// SDRAM
input logic enable_sdram,
input logic sdram_clock, // 50MHz
Expand Down Expand Up @@ -156,6 +176,8 @@ module CHIPSET (

PERIPHERALS u_PERIPHERALS (
.clock (clock),
.clk_sys (clk_sys),
.clk_uart (clk_uart),
.peripheral_clock (peripheral_clock),
.reset (reset),
.interrupt_to_cpu (interrupt_to_cpu),
Expand Down Expand Up @@ -196,7 +218,23 @@ module CHIPSET (
.clk_en_opl2 (clk_en_opl2),
.jtopl2_snd_e (jtopl2_snd_e),
.adlibhide (adlibhide),
<<<<<<< Updated upstream
.tandy_snd_e (tandy_snd_e)
=======
.tandy_snd_e (tandy_snd_e),
.ioctl_download (ioctl_download),
.ioctl_index (ioctl_index),
.ioctl_wr (ioctl_wr),
.ioctl_addr (ioctl_addr),
.ioctl_data (ioctl_data),
.uart_rx (uart_rx),
.uart_tx (uart_tx),
.uart_cts_n (uart_cts),
.uart_dcd_n (uart_dcd),
.uart_dsr_n (uart_dsr),
.uart_rts_n (uart_rts),
.uart_dtr_n (uart_dtr)
>>>>>>> Stashed changes

);

Expand Down

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