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changed chipset clock to 50 mhz and rework (by @kitune-san)
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* changed chipset clock to 50 mhz.
* Added false_path.
* Change peripheral_clock signal.
* Added F/F to the write process to the EMS memory to resolve timing co…
* Add 2-stage F/F between bus and video module.
* Changed 8253 timer_clock signal.
* Fixed F/F clocks.
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@spark2k06
spark2k06 committed Aug 4, 2022
1 parent b838184 commit afd39c8
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Showing 6 changed files with 230 additions and 64 deletions.
36 changes: 35 additions & 1 deletion PCXT.sdc
View file
Expand Up @@ -4,17 +4,51 @@ derive_clock_uncertainty
# core specific constraints
# Clocks
set CLOCK_CORE {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}
set CLOCK_CHIP {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[5].output_counter|divclk}
set CLOCK_UART {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk}
set CLOCK_14_318 {emu|clk_14_318|q}
set CLOCK_4_77 {emu|clk_normal|clk_out|q}
set PCLK {emu|peripheral_clock|q}

create_generated_clock -name clk_14_318 -source [get_pins {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk}] -divide_by 2 [get_pins $CLOCK_14_318]
create_generated_clock -name clk_4_77 -source [get_pins $CLOCK_14_318] -divide_by 3 -duty_cycle 33 [get_pins $CLOCK_4_77]
create_generated_clock -name peripheral_clock -source [get_pins $CLOCK_4_77] -divide_by 2 [get_pins $PCLK]
create_generated_clock -name SDRAM_CLK -source { FPGA_CLK2_50 } [get_ports { SDRAM_CLK }]
create_generated_clock -name SDRAM_CLK -source [get_pins $CLOCK_CHIP] [get_ports { SDRAM_CLK }]

set_false_path -to [get_registers {emu:emu|clk_cpu_ff_1 emu:emu|pclk_ff_1 emu:emu|clk_opl2_ff_1}]

# status signal
set_false_path -from [get_registers {emu:emu|hps_io:hps_io|status[3] emu:emu|hps_io:hps_io|status[4] emu:emu|hps_io:hps_io|status[7]}]

# UART
set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks $CLOCK_UART]
set_false_path -from [get_clocks $CLOCK_UART] -to [get_clocks $CLOCK_CHIP]

# VIDEO
set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_address[*] \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_data[*] \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_write_n \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_read_n \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_address_enable_n}] \
-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_address_1[*] \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_data_1[*] \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_write_n_1 \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_read_n_1 \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_address_enable_n_1 \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_address_1[*] \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_data_1[*] \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_write_n_1 \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_read_n_1 \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_address_enable_n_1}] 10

set_max_delay -to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|MDA_CRTC_DOUT_1[*] \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|MDA_CRTC_OE_1 \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|CGA_CRTC_DOUT_1[*] \
emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|CGA_CRTC_OE_1}] 10

# SDRAM
set_input_delay -clock { SDRAM_CLK } -max 6 [get_ports { SDRAM_DQ[*] }]
set_input_delay -clock { SDRAM_CLK } -min 3 [get_ports { SDRAM_DQ[*] }]
set_output_delay -clock { SDRAM_CLK } -max 2 [get_ports { SDRAM_DQ[*] SDRAM_DQM* SDRAM_A[*] SDRAM_n* SDRAM_BA[*] SDRAM_CKE }]
set_output_delay -clock { SDRAM_CLK } -min 1.5 [get_ports { SDRAM_DQ[*] SDRAM_DQM* SDRAM_A[*] SDRAM_n* SDRAM_BA[*] SDRAM_CKE }]

33 changes: 21 additions & 12 deletions PCXT.sv
View file
Expand Up @@ -178,7 +178,7 @@ assign USER_OUT = '1;
//assign {UART_RTS, UART_TXD, UART_DTR} = 0;
//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign SDRAM_CLK = CLK_50M;
assign SDRAM_CLK = clk_chipset;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;


Expand Down Expand Up @@ -292,7 +292,7 @@ wire adlibhide = status[10];

hps_io #(.CONF_STR(CONF_STR), .PS2DIV(2000), .PS2WE(1)) hps_io
(
.clk_sys(CLK_50M),
.clk_sys(clk_chipset),
.HPS_BUS(HPS_BUS),
.EXT_BUS(),
.gamma_bus(gamma_bus),
Expand Down Expand Up @@ -346,7 +346,9 @@ reg clk_14_318 = 1'b0;
reg clk_7_16 = 1'b0;
wire clk_4_77;
wire clk_cpu;
wire pclk;
wire clk_opl2;
wire clk_chipset;
wire peripheral_clock;

pll pll
Expand All @@ -358,6 +360,7 @@ pll pll
.outclk_2(clk_28_636),
.outclk_3(clk_uart),
.outclk_4(clk_opl2),
.outclk_5(clk_chipset),
.locked(pll_locked)
);

Expand Down Expand Up @@ -407,18 +410,24 @@ always @(posedge clk_4_77)
logic clk_cpu_ff_1;
logic clk_cpu_ff_2;

always @(posedge clk_100) begin
logic pclk_ff_1;
logic pclk_ff_2;

always @(posedge clk_chipset) begin
clk_cpu_ff_1 <= clk_4_77;
clk_cpu_ff_2 <= clk_cpu_ff_1;
clk_cpu <= clk_cpu_ff_2;
pclk_ff_1 <= peripheral_clock;
pclk_ff_2 <= pclk_ff_1;
pclk <= pclk_ff_2;
end

logic clk_opl2_ff_1;
logic clk_opl2_ff_2;
logic clk_opl2_ff_3;
logic cen_opl2;

always @(posedge clk_100) begin
always @(posedge clk_chipset) begin
clk_opl2_ff_1 <= clk_opl2;
clk_opl2_ff_2 <= clk_opl2_ff_1;
clk_opl2_ff_3 <= clk_opl2_ff_2;
Expand Down Expand Up @@ -456,14 +465,14 @@ logic reset_cpu_ff = 1'b1;
logic reset_cpu = 1'b1;
logic [15:0] reset_cpu_count = 16'h0000;

always @(negedge clk_100, posedge reset) begin
always @(negedge clk_chipset, posedge reset) begin
if (reset)
reset_cpu_ff <= 1'b1;
else
reset_cpu_ff <= reset;
end

always @(negedge clk_100, posedge reset) begin
always @(negedge clk_chipset, posedge reset) begin
if (reset) begin
reset_cpu <= 1'b1;
reset_cpu_count <= 16'h0000;
Expand Down Expand Up @@ -518,7 +527,7 @@ end
logic device_clock_ff;
logic device_clock;

always_ff @(negedge clk_cpu, posedge reset)
always_ff @(negedge clk_chipset, posedge reset)
begin
if (reset) begin
device_clock_ff <= 1'b0;
Expand All @@ -537,7 +546,7 @@ end
logic device_data_ff;
logic device_data;

always_ff @(negedge clk_cpu, posedge reset)
always_ff @(negedge clk_chipset, posedge reset)
begin
if (reset) begin
device_data_ff <= 1'b0;
Expand Down Expand Up @@ -575,10 +584,10 @@ end
assign port_c_in[3:0] = port_b_out[3] ? sw[7:4] : sw[3:0];

CHIPSET u_CHIPSET (
.clock (clk_100),
.clock (clk_chipset),
.cpu_clock (clk_cpu),
.clk_sys (CLK_50M),
.peripheral_clock (peripheral_clock),
.clk_sys (clk_chipset),
.peripheral_clock (pclk),

.reset (reset_cpu),
.sdram_reset (reset),
Expand Down Expand Up @@ -733,7 +742,7 @@ end
wire uart_dsr = UART_DSR;
wire uart_dcd = UART_DTR;

always @(posedge clk_cpu) begin
always @(posedge clk_100) begin
if (address_latch_enable)
cpu_address <= cpu_ad_out;
else
Expand Down

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