Setting timings for tandy_16_gfx mode

spark2k06 · Aug 11, 2022 · f89ae7d · f89ae7d
1 parent 37fead8
commit f89ae7d
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Showing 6 changed files with 23 additions and 11 deletions.
diff --git a/PCXT.sv b/PCXT.sv
@@ -588,7 +588,7 @@ end
         .cpu_clock                            (clk_cpu),
 		  .clk_sys                            (clk_chipset),
 		  .peripheral_clock                   (pclk),
-
+		  .color										  (screen_mode == 3'd0),
         .reset                              (reset_cpu),
         .sdram_reset                        (reset),
         .cpu_address                        (cpu_address),

diff --git a/rtl/KFPC-XT/HDL/Chipset.sv b/rtl/KFPC-XT/HDL/Chipset.sv
@@ -7,6 +7,7 @@ module CHIPSET (
     input   logic           cpu_clock,
 	 input   logic           clk_sys,
     input   logic           peripheral_clock,
+	 input   logic           color,
     input   logic           reset,
     input   logic           sdram_reset,
     // CPU
@@ -227,6 +228,7 @@ module CHIPSET (
 		  .clk_sys                            (clk_sys),
 		  .clk_uart                           (clk_uart),
         .peripheral_clock                   (peripheral_clock),
+		  .color                              (color),
         .reset                              (reset),
         .interrupt_to_cpu                   (interrupt_to_cpu),
         .interrupt_acknowledge_n            (interrupt_acknowledge_n),

diff --git a/rtl/KFPC-XT/HDL/Peripherals.sv b/rtl/KFPC-XT/HDL/Peripherals.sv
@@ -8,6 +8,7 @@ module PERIPHERALS #(
     input   logic           clock,
 	 input   logic           clk_sys,
     input   logic           peripheral_clock,	 
+	 input   logic           color,
     input   logic           reset,
     // CPU
     output  logic           interrupt_to_cpu,
@@ -727,7 +728,8 @@ module PERIPHERALS #(
         .dbl_video                  (vga_video),                // scandoubler
 		  .splashscreen               (splashscreen),
         .thin_font                  (thin_font),
-		  .tandy_video                (tandy_video)
+		  .tandy_video                (tandy_video),
+		  .color                      (color)
     );
 
     always_ff @(posedge clock) begin

diff --git a/rtl/video/cga.v b/rtl/video/cga.v
@@ -41,7 +41,8 @@ module cga(
 
 	 input splashscreen,
     input thin_font,
-	 input tandy_video
+	 input tandy_video,
+	 input color
     );
 
     parameter MDA_70HZ = 0;
@@ -278,7 +279,9 @@ endgenerate
         .cursor(cursor),
         .mem_addr(crtc_addr),
         .row_addr(row_addr),
-        .line_reset(line_reset)
+        .line_reset(line_reset),
+		  .tandy_16_gfx(tandy_16_mode & grph_mode & hres_mode),
+		  .color(color)
     );
 
     // CGA 80 column timings
@@ -318,7 +321,8 @@ endgenerate
         .disp_pipeline(disp_pipeline),
         .isa_op_enable(isa_op_enable),
         .hclk(hclk),
-        .lclk(lclk)
+        .lclk(lclk),
+		  .tandy_16_gfx(tandy_16_mode & grph_mode & hres_mode)
     );
 
     // Pixel pusher

diff --git a/rtl/video/cga_sequencer.v b/rtl/video/cga_sequencer.v
@@ -20,7 +20,8 @@ module cga_sequencer(
     output disp_pipeline,
     output isa_op_enable,
     output hclk,
-    output lclk
+    output lclk,
+	 input tandy_16_gfx
     );
 
     wire crtc_clk_int;
@@ -50,7 +51,8 @@ module cga_sequencer(
     assign vram_read_char = (clkdiv == 5'd2) || (hres_mode ? (clkdiv == 5'd18) : 0);
     assign vram_read_att = (clkdiv == 5'd3) || (hres_mode ? (clkdiv == 5'd19) : 0);
     assign charrom_read = (clkdiv == 5'd3) || (hres_mode ? (clkdiv == 5'd19) : 0);// 3 and 19?
-    assign disp_pipeline = (clkdiv == 5'd4) || (hres_mode ? (clkdiv == 5'd20) : 0);
+    assign disp_pipeline = (clkdiv == (tandy_16_gfx ? 5'd7 : 5'd4)) || (hres_mode ? (clkdiv == (tandy_16_gfx ? 5'd23 : 5'd20)) : 0);
+	 //assign disp_pipeline = (clkdiv == 5'd7) || (hres_mode ? (clkdiv == 5'd23) : 0);// 3 and 19?
     assign crtc_clk = crtc_clk_int;
     assign clk_seq = clkdiv;
     // Leave a gap of at least 2 cycles between the end of ISA operation and

diff --git a/rtl/video/crtc6845.v b/rtl/video/crtc6845.v
@@ -30,7 +30,9 @@ module crtc6845(
     output cursor,
     output [13:0] mem_addr,
     output [4:0] row_addr,
-    output line_reset);
+    output line_reset,
+	 input tandy_16_gfx,
+	 input color);
 
     parameter H_TOTAL = 0;
     parameter H_DISP = 0;
@@ -139,7 +141,7 @@ module crtc6845(
     reg hs = 1'b0;
     reg hdisp = 1'b1;
     reg vdisp = 1'b1;
-    reg [6:0] hdisp_del;
+    reg [12:0] hdisp_del;
 
     wire cur_on;
     wire blink;
@@ -150,7 +152,7 @@ module crtc6845(
     assign vsync = vs;
     assign hsync = hs;
     assign display_enable = hdisp & vdisp;
-    assign hblank = ~hdisp_del[5];
+    assign hblank = tandy_16_gfx ? ~hdisp_del[color ? 9 : 11] : ~hdisp_del[color ? 5 : 7];
     assign vblank = ~vdisp;
 
     assign row_addr = v_scancount;
@@ -162,7 +164,7 @@ module crtc6845(
     // Horizontal counter
     always @ (posedge clk)
     begin
-        hdisp_del <= {hdisp_del[5], hdisp_del[4], hdisp_del[3], hdisp_del[2], hdisp_del[1], hdisp_del[0], hdisp};		  	  
+        hdisp_del <= {hdisp_del[11], hdisp_del[10], hdisp_del[9], hdisp_del[8], hdisp_del[7], hdisp_del[6], hdisp_del[5], hdisp_del[4], hdisp_del[3], hdisp_del[2], hdisp_del[1], hdisp_del[0], hdisp};		  	  
         if (divclk) begin
             if (h_count == h_total) begin
                 h_count <= 8'd0;