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RTL codegen "line" error #1403

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merged 7 commits into from Oct 19, 2023
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carljohnsen
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The issue in #1383 uncovered flaws in the RTL samples:

  1. Unsupported RTL configurations not failing gracefully.
    The specific error arose when an RTL tasklet tried to access a stream during simulation mode, which is currently not supported in simulation mode, as the produced Verilator code does not mimick actual behaviour, resulting in a deadlock. Current "fix" is to emit this shortcoming as a comment in the resulting code. It should not always fail (hence the emission to a comment), since the RTL code generator is partially used by the Xilinx code generator, leading to said faulty code to be omitted anyways; at least for the samples/tests that reach this point.
  2. The samples (at least not all of them) did not set the required DaCe configuration entries.
    Some of the samples did correctly use with dace.config.set_temporary(), forcing them to run as they're inteded to be run. This has been changed, so all RTL samples run in their respective modes. Furthermore, some of the samples did not have this requirement mentioned in their comments, which has also been fixed.

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@tbennun tbennun left a comment

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Thanks for the fix! Two minor comments.

Comment on lines 105 to 108
elif isinstance(arr, data.Stream):
# TODO Streams are currently unsupported, as the proper behaviour has to be implemented to avoid deadlocking.
line: str = "// Unsupported read from ({}) variable '{}' from stream '{}'".format(
dst_node.in_connectors[edge.dst_conn].ctype, edge.dst_conn, edge.src_conn)
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Is it not better to raise a verbose error or at least a warning in this case? It will likely produce erroneous code.

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An error no, as the RTL backend is used by the Xilinx backend, which may hit this case without using the faulty code. I've further elaborated this in the comment. I've added the information as a warning as well.

Comment on lines 2 to 5
"""
Two sequential RTL tasklets connected through a memlet.
"""
# Copyright 2019-2023 ETH Zurich and the DaCe authors. All rights reserved.
#
# Two sequential RTL tasklets connected through a memlet.
#
# It is intended for running simulation xilinx targets.
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The previous docstring version is the standard way of defining a file.

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Ah, right, I see! I've reverted them "back" to this format! :)

@tbennun tbennun merged commit 8402e52 into spcl:master Oct 19, 2023
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@BenWeber42 BenWeber42 mentioned this pull request Oct 27, 2023
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2 participants