8-bit-ALU-in-Verilog

Introduction

ALU performs arithmetic and logic operations. It is also one of the most fundamental units of many computing circuits, including the central processing unit (CPU) of computers, and the graphic processing unit (GPU) of video cards.

In this repo you can find independent modules that can perform 8-bit arithmetic operations like ADDITION, SUBTRACTION and logic operations like AND, OR, XOR. In the end all combine to form an ALU.

Inputs of an ALU are primarily the operands which are the data to be operated on. In addition, an ALU has opcodes (operation codes) as inputs to control the type of operation the ALU shall perform.

Pin description

Opcodes

Internal View Of ALU

PDF File

Output

Output generated using testbench

Output generated using waveform file

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
.qsys_edit		.qsys_edit
assets		assets
db		db
incremental_db		incremental_db
output_files		output_files
report		report
simulation		simulation
.gitignore		.gitignore
README.md		README.md
Waveform.vwf		Waveform.vwf
add_4bit.v		add_4bit.v
add_4bit.v.bak		add_4bit.v.bak
add_8bit.v		add_8bit.v
add_8bit.v.bak		add_8bit.v.bak
add_subtract_8bit.v		add_subtract_8bit.v
add_subtract_8bit.v.bak		add_subtract_8bit.v.bak
add_subtract_8bit.vwf		add_subtract_8bit.vwf
alu8bit.v		alu8bit.v
alu8bit.v.bak		alu8bit.v.bak
alu_8bit.qpf		alu_8bit.qpf
alu_8bit.qsf		alu_8bit.qsf
alu_8bit.qws		alu_8bit.qws
alu_8bit.v.bak		alu_8bit.v.bak
alu_8bit_assignment_defaults.qdf		alu_8bit_assignment_defaults.qdf
alu_8bit_nativelink_simulation.rpt		alu_8bit_nativelink_simulation.rpt
and_gate4.v		and_gate4.v
and_gate4.v.bak		and_gate4.v.bak
and_gate8.v		and_gate8.v
and_gate8.v.bak		and_gate8.v.bak
c5_pin_model_dump.txt		c5_pin_model_dump.txt
dec_8bit.v		dec_8bit.v
dec_8bit.v.bak		dec_8bit.v.bak
exor_gate4.v		exor_gate4.v
exor_gate8.v		exor_gate8.v
exor_gate8.v.bak		exor_gate8.v.bak
inc_8bit.v		inc_8bit.v
inc_8bit.v.bak		inc_8bit.v.bak
mux38.v		mux38.v
mux38.v.bak		mux38.v.bak
not_gate4.v		not_gate4.v
not_gate4.v.bak		not_gate4.v.bak
not_gate8.v		not_gate8.v
not_gate8.v.bak		not_gate8.v.bak
or_gate4.v		or_gate4.v
or_gate4.v.bak		or_gate4.v.bak
or_gate8.v		or_gate8.v
or_gate8.v.bak		or_gate8.v.bak
qar_info.json		qar_info.json
shift_8bit.v		shift_8bit.v
shift_8bit.v.bak		shift_8bit.v.bak
sub_8bit.v		sub_8bit.v
testbench_alu.v		testbench_alu.v
testbench_alu.v.bak		testbench_alu.v.bak

SravanChittupalli/8-bit-ALU-in-verilog

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8-bit-ALU-in-Verilog

Introduction

Pin description

Opcodes

Internal View Of ALU

Output

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