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Regarding setting LUTs: right now the way we set initial values in LUTs is by specifying values for the LUT in a Spatial app. When we want big LUTs, the time spent on synthesizing these LUTs in Spatial becomes very long. Instead we could potentially use Vivado's SRAM init for these LUTs by using something that looks like: https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/pce_p_initialize_blockram.htm.
The text was updated successfully, but these errors were encountered:
It seems that our LUT template is implemented as a list of registers instead of a chisel ROM, and that would very likely prevent the downstream synthesizer to recognize the LUT module as a ROM. Is there a reason that we wanted to use registers for LUTs instead of ROM?
Nope you can change it to ROM. I think we only used RegFiles with init values to create LUTs in the app code at one point, so both nodes called the same template when they got split.
Regarding setting LUTs: right now the way we set initial values in LUTs is by specifying values for the LUT in a Spatial app. When we want big LUTs, the time spent on synthesizing these LUTs in Spatial becomes very long. Instead we could potentially use Vivado's SRAM init for these LUTs by using something that looks like: https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/pce_p_initialize_blockram.htm.
The text was updated successfully, but these errors were encountered: