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clk: starfive: pll: Remove high frequency of PLL0
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Remove high frequency of PLL0 and make sure PLL0 max frequency is 1.5GHz.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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SFxingyuwu committed Dec 15, 2022
1 parent 25fbb71 commit 67d314a
Showing 1 changed file with 3 additions and 23 deletions.
26 changes: 3 additions & 23 deletions drivers/clk/starfive/clk-starfive-jh7110-pll.h
Expand Up @@ -125,9 +125,7 @@ enum starfive_pll0_freq_value {
PLL0_FREQ_1000_VALUE = 1000000000,
PLL0_FREQ_1250_VALUE = 1250000000,
PLL0_FREQ_1375_VALUE = 1375000000,
PLL0_FREQ_1500_VALUE = 1500000000,
PLL0_FREQ_1625_VALUE = 1625000000,
PLL0_FREQ_1750_VALUE = 1750000000
PLL0_FREQ_1500_VALUE = 1500000000
};

enum starfive_pll0_freq {
Expand All @@ -140,9 +138,7 @@ enum starfive_pll0_freq {
PLL0_FREQ_1250,
PLL0_FREQ_1375,
PLL0_FREQ_1500,
PLL0_FREQ_1625,
PLL0_FREQ_1750,
PLL0_FREQ_MAX
PLL0_FREQ_MAX = PLL0_FREQ_1500
};

enum starfive_pll1_freq_value {
Expand All @@ -164,7 +160,7 @@ enum starfive_pll2_freq {
};

static const struct starfive_pll_syscon_value
jh7110_pll0_syscon_freq[PLL0_FREQ_MAX] = {
jh7110_pll0_syscon_freq[] = {
[PLL0_FREQ_375] = {
.freq = PLL0_FREQ_375_VALUE,
.prediv = 8,
Expand Down Expand Up @@ -237,22 +233,6 @@ static const struct starfive_pll_syscon_value
.dacpd = 1,
.dsmpd = 1,
},
[PLL0_FREQ_1625] = {
.freq = PLL0_FREQ_1625_VALUE,
.prediv = 24,
.fbdiv = 1625,
.postdiv1 = 1,
.dacpd = 1,
.dsmpd = 1,
},
[PLL0_FREQ_1750] = {
.freq = PLL0_FREQ_1750_VALUE,
.prediv = 12,
.fbdiv = 875,
.postdiv1 = 1,
.dacpd = 1,
.dsmpd = 1,
},
};

static const struct starfive_pll_syscon_value
Expand Down

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