Merge branch 'CR_10259_add_amp_minda' into 'jh7110-master'

CR_10259 spl: amp: Enable UART2 and move rtos image to memory See merge request sdk/u-boot!83
starfive-tech · Apr 30, 2024 · 7572e01 · 7572e01
2 parents 466022f + 75814d6
commit 7572e01
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Showing 6 changed files with 177 additions and 3 deletions.
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
@@ -7,8 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_DEVKITS) += starfive_devkits.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += starfive_visionfive2.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_DEVKITS) += starfive_devkits.dtb starfive_jh7110-amp.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += starfive_visionfive2.dtb starfive_jh7110-amp.dtb
 dtb-$(CONFIG_TARGET_STARFIVE_EVB) += starfive_evb.dtb
 
 targets += $(dtb-y)

diff --git a/arch/riscv/dts/starfive_jh7110-amp-u-boot.dtsi b/arch/riscv/dts/starfive_jh7110-amp-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#if defined(CONFIG_TARGET_STARFIVE_VISIONFIVE2)
+#include "starfive_visionfive2-u-boot.dtsi"
+#endif
+#if defined(CONFIG_TARGET_STARFIVE_DEVKITS)
+#include "starfive_devkits-u-boot.dtsi"
+#endif
+
+/ {
+	config {
+		amp,rtos-offset = <0x330000>;
+		amp,rtos-code-base = <0x6e800000>;
+	};
+};
diff --git a/arch/riscv/dts/starfive_jh7110-amp.dts b/arch/riscv/dts/starfive_jh7110-amp.dts
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#if defined(CONFIG_TARGET_STARFIVE_VISIONFIVE2)
+#include "starfive_visionfive2.dts"
+#endif
+#if defined(CONFIG_TARGET_STARFIVE_DEVKITS)
+#include "starfive_devkits.dts"
+#endif
+
+/ {
+	chosen {
+		opensbi-domains {
+			compatible = "opensbi,domain,config";
+
+			rpmsg_shmem: rpmsg_shmem {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x6e400000>;
+				order = <22>;
+			};
+
+			rtcode: rtcode {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x6e800000>;
+				order = <23>;
+			};
+
+			rtheap: rtheap {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x6f000000>;
+				order = <24>;
+			};
+
+			dram0: dram0 {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x40000000>;
+				order = <30>;
+			};
+
+			dram1: dram1 {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x80000000>;
+				order = <31>;
+			};
+
+			allmem: allmem {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x0>;
+				order = <64>;
+			};
+
+			udomain: u-domain {
+				compatible = "opensbi,domain,instance";
+				possible-harts = <&cpu0 &cpu1 &cpu2 &cpu3>;
+				regions = <&rtcode 0x0>, <&rtheap 0x0>, <&allmem 0x3f>;
+				next-addr = <0x0 0x40200000>;
+				boot-hart = <&cpu1>;
+				system-reset-allowed;
+				system-suspend-allowed;
+			};
+
+			rtdomain: rt-domain {
+				compatible = "opensbi,domain,instance";
+				possible-harts = <&cpu4>;
+				regions = <&rpmsg_shmem 0x3f>, <&rtcode 0x3f>, <&rtheap 0x3f>,
+					<&dram1 0x0>, <&allmem 0x3f>;
+				boot-hart = <&cpu4>;
+				next-arg1 = <0x0 0x0>;
+				next-addr = <0x0 0x6e800000>;
+				next-mode = <0x1>;
+			};
+		};
+	};
+};
+
+&cpu0 {
+	opensbi-domain = <&udomain>;
+};
+
+&cpu1 {
+	opensbi-domain = <&udomain>;
+};
+
+&cpu2 {
+	opensbi-domain = <&udomain>;
+};
+
+&cpu3 {
+	opensbi-domain = <&udomain>;
+};
+
+&cpu4 {
+	opensbi-domain = <&rtdomain>;
+};
+
+&gmac1 {
+	status = "disabled";
+};
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
@@ -114,5 +114,8 @@
 #define CLK_QSPI_REF_SW_SHIFT	24
 #define CLK_QSPI_REF_SW_MASK	0x1000000U
 
+#define CLK_UART2_APB_OFFSET   0x254
+#define CLK_UART2_CORE_OFFSET  0x258
+#define CLK_RSTN_3_OFFSET      0x300
 #endif /* __STARFIVE_JH7110_REGS_H */
 
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
@@ -18,6 +18,8 @@
 
 #define MODE_SELECT_REG		0x1702002c
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int spl_board_init_f(void)
 {
 	int ret;
@@ -186,4 +188,36 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
+static void spl_enable_uart2(void)
+{
+	/* uart2 clock */
+	setbits_le32(SYS_CRG_BASE + CLK_UART2_APB_OFFSET, BIT(31));
+	setbits_le32(SYS_CRG_BASE + CLK_UART2_CORE_OFFSET, BIT(31));
+	clrsetbits_le32(SYS_CRG_BASE + CLK_RSTN_3_OFFSET, BIT(23) | BIT(24), 0);
+
+	/*uart2 tx*/
+	SYS_IOMUX_DOEN(43, LOW);
+	SYS_IOMUX_DOUT(43, 0x4f);
+	SYS_IOMUX_SET_DS(43, 3);
+	/*uart2 rx*/
+	SYS_IOMUX_DOEN(42, HIGH);
+	SYS_IOMUX_DIN(42, 62);
+}
 
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	unsigned long rtos_offset, rtos_image_addr;
+	unsigned long rtos_base;
+
+	rtos_base = fdtdec_get_config_int(gd->fdt_blob,
+					  "amp,rtos-code-base", 0);
+	rtos_offset = fdtdec_get_config_int(gd->fdt_blob,
+					    "amp,rtos-offset", 0);
+
+	if (rtos_base && rtos_offset) {
+		spl_enable_uart2();
+		rtos_image_addr = CONFIG_SPL_OPENSBI_LOAD_ADDR + rtos_offset;
+		memcpy((void *)rtos_base, (void *)(rtos_image_addr),
+		       spl_image->size - rtos_offset);
+	}
+}
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -32,6 +32,8 @@
 
 #define CPU_VOL_BINNING_OFFSET 0x7fc
 
+DECLARE_GLOBAL_DATA_PTR;
+
 enum {
 	BOOT_FLASH =	0,
 	BOOT_SD,
@@ -422,7 +424,9 @@ int board_init(void)
 int board_late_init(void)
 {
 	struct udevice *dev;
-	int ret;
+	int ret, offset;
+	u8 mac0[6], mac1[6];
+	u64 share_ram_addr;
 
 	get_boot_mode();
 
@@ -443,6 +447,20 @@ int board_late_init(void)
 	if (ret)
 		goto err;
 
+	/* AMP case : write MAC to share ram */
+	offset = fdt_path_offset(gd->fdt_blob,
+				 "/chosen/opensbi-domains/rpmsg_shmem");
+	if (offset >= 0) {
+		share_ram_addr =
+			fdtdec_get_uint64(gd->fdt_blob, offset, "base", 0);
+		if (share_ram_addr) {
+			eth_env_get_enetaddr("eth0addr", mac0);
+			eth_env_get_enetaddr("eth1addr", mac1);
+			memcpy((void *)share_ram_addr, mac0, 6);
+			memcpy((void *)(share_ram_addr + 8), mac1, 6);
+		}
+	}
+
 err:
 	return 0;
 }