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spu.cpp
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spu.cpp
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#include "spu.h"
#include "cdrom.h"
#include "common/audio_stream.h"
#include "common/file_system.h"
#include "common/log.h"
#include "common/state_wrapper.h"
#include "common/wav_writer.h"
#include "dma.h"
#include "host_interface.h"
#include "imgui.h"
#include "interrupt_controller.h"
#include "system.h"
Log_SetChannel(SPU);
SPU g_spu;
SPU::SPU() = default;
SPU::~SPU() = default;
void SPU::Initialize()
{
// (X * D) / N / 768 -> (X * D) / (N * 768)
m_cpu_ticks_per_spu_tick = System::ScaleTicksToOverclock(SYSCLK_TICKS_PER_SPU_TICK);
m_cpu_tick_divider = static_cast<TickCount>(g_settings.cpu_overclock_numerator * SYSCLK_TICKS_PER_SPU_TICK);
m_tick_event = TimingEvents::CreateTimingEvent(
"SPU Sample", m_cpu_ticks_per_spu_tick, m_cpu_ticks_per_spu_tick,
[](void* param, TickCount ticks, TickCount ticks_late) { static_cast<SPU*>(param)->Execute(ticks); }, this, false);
m_transfer_event = TimingEvents::CreateTimingEvent(
"SPU Transfer", TRANSFER_TICKS_PER_HALFWORD, TRANSFER_TICKS_PER_HALFWORD,
[](void* param, TickCount ticks, TickCount ticks_late) { static_cast<SPU*>(param)->ExecuteTransfer(ticks); }, this,
false);
m_audio_stream = g_host_interface->GetAudioStream();
Reset();
}
void SPU::CPUClockChanged()
{
// (X * D) / N / 768 -> (X * D) / (N * 768)
m_cpu_ticks_per_spu_tick = System::ScaleTicksToOverclock(SYSCLK_TICKS_PER_SPU_TICK);
m_cpu_tick_divider = static_cast<TickCount>(g_settings.cpu_overclock_numerator * SYSCLK_TICKS_PER_SPU_TICK);
m_ticks_carry = 0;
UpdateEventInterval();
}
void SPU::Shutdown()
{
m_tick_event.reset();
m_transfer_event.reset();
m_dump_writer.reset();
m_audio_stream = nullptr;
}
void SPU::Reset()
{
m_ticks_carry = 0;
m_SPUCNT.bits = 0;
m_SPUSTAT.bits = 0;
m_transfer_address = 0;
m_transfer_address_reg = 0;
m_irq_address = 0;
m_capture_buffer_position = 0;
m_main_volume_left_reg.bits = 0;
m_main_volume_right_reg.bits = 0;
m_main_volume_left = {};
m_main_volume_right = {};
m_cd_audio_volume_left = 0;
m_cd_audio_volume_right = 0;
m_external_volume_left = 0;
m_external_volume_right = 0;
m_key_on_register = 0;
m_key_off_register = 0;
m_endx_register = 0;
m_pitch_modulation_enable_register = 0;
m_noise_mode_register = 0;
m_noise_count = 0;
m_noise_level = 1;
m_reverb_on_register = 0;
m_reverb_registers = {};
m_reverb_registers.mBASE = 0;
m_reverb_base_address = m_reverb_current_address = ZeroExtend32(m_reverb_registers.mBASE) << 2;
m_reverb_downsample_buffer = {};
m_reverb_upsample_buffer = {};
m_reverb_resample_buffer_position = 0;
for (u32 i = 0; i < NUM_VOICES; i++)
{
Voice& v = m_voices[i];
v.current_address = 0;
std::fill_n(v.regs.index, NUM_VOICE_REGISTERS, u16(0));
v.counter.bits = 0;
v.current_block_flags.bits = 0;
v.is_first_block = 0;
v.current_block_samples.fill(s16(0));
v.adpcm_last_samples.fill(s32(0));
v.adsr_envelope.Reset(0, false, false);
v.adsr_phase = ADSRPhase::Off;
v.adsr_target = 0;
v.has_samples = false;
v.ignore_loop_address = false;
}
m_transfer_fifo.Clear();
m_transfer_event->Deactivate();
m_ram.fill(0);
UpdateEventInterval();
}
bool SPU::DoState(StateWrapper& sw)
{
sw.Do(&m_ticks_carry);
sw.Do(&m_SPUCNT.bits);
sw.Do(&m_SPUSTAT.bits);
sw.Do(&m_transfer_control.bits);
sw.Do(&m_transfer_address);
sw.Do(&m_transfer_address_reg);
sw.Do(&m_irq_address);
sw.Do(&m_capture_buffer_position);
sw.Do(&m_main_volume_left_reg.bits);
sw.Do(&m_main_volume_right_reg.bits);
sw.DoPOD(&m_main_volume_left);
sw.DoPOD(&m_main_volume_right);
sw.Do(&m_cd_audio_volume_left);
sw.Do(&m_cd_audio_volume_right);
sw.Do(&m_external_volume_left);
sw.Do(&m_external_volume_right);
sw.Do(&m_key_on_register);
sw.Do(&m_key_off_register);
sw.Do(&m_endx_register);
sw.Do(&m_pitch_modulation_enable_register);
sw.Do(&m_noise_mode_register);
sw.Do(&m_noise_count);
sw.Do(&m_noise_level);
sw.Do(&m_reverb_on_register);
sw.Do(&m_reverb_base_address);
sw.Do(&m_reverb_current_address);
sw.Do(&m_reverb_registers.vLOUT);
sw.Do(&m_reverb_registers.vROUT);
sw.Do(&m_reverb_registers.mBASE);
sw.DoArray(m_reverb_registers.rev, NUM_REVERB_REGS);
for (u32 i = 0; i < 2; i++)
sw.DoArray(m_reverb_downsample_buffer.data(), m_reverb_downsample_buffer.size());
for (u32 i = 0; i < 2; i++)
sw.DoArray(m_reverb_upsample_buffer.data(), m_reverb_upsample_buffer.size());
sw.Do(&m_reverb_resample_buffer_position);
for (u32 i = 0; i < NUM_VOICES; i++)
{
Voice& v = m_voices[i];
sw.Do(&v.current_address);
sw.DoArray(v.regs.index, NUM_VOICE_REGISTERS);
sw.Do(&v.counter.bits);
sw.Do(&v.current_block_flags.bits);
sw.DoEx(&v.is_first_block, 47, false);
sw.DoArray(&v.current_block_samples[NUM_SAMPLES_FROM_LAST_ADPCM_BLOCK], NUM_SAMPLES_PER_ADPCM_BLOCK);
sw.DoArray(&v.current_block_samples[0], NUM_SAMPLES_FROM_LAST_ADPCM_BLOCK);
sw.Do(&v.adpcm_last_samples);
sw.Do(&v.last_volume);
sw.DoPOD(&v.left_volume);
sw.DoPOD(&v.right_volume);
sw.DoPOD(&v.adsr_envelope);
sw.Do(&v.adsr_phase);
sw.Do(&v.adsr_target);
sw.Do(&v.has_samples);
sw.Do(&v.ignore_loop_address);
}
sw.Do(&m_transfer_fifo);
sw.DoBytes(m_ram.data(), RAM_SIZE);
if (sw.IsReading())
{
UpdateEventInterval();
UpdateTransferEvent();
}
return !sw.HasError();
}
u16 SPU::ReadRegister(u32 offset)
{
switch (offset)
{
case 0x1F801D80 - SPU_BASE:
return m_main_volume_left_reg.bits;
case 0x1F801D82 - SPU_BASE:
return m_main_volume_right_reg.bits;
case 0x1F801D84 - SPU_BASE:
return m_reverb_registers.vLOUT;
case 0x1F801D86 - SPU_BASE:
return m_reverb_registers.vROUT;
case 0x1F801D88 - SPU_BASE:
return Truncate16(m_key_on_register);
case 0x1F801D8A - SPU_BASE:
return Truncate16(m_key_on_register >> 16);
case 0x1F801D8C - SPU_BASE:
return Truncate16(m_key_off_register);
case 0x1F801D8E - SPU_BASE:
return Truncate16(m_key_off_register >> 16);
case 0x1F801D90 - SPU_BASE:
return Truncate16(m_pitch_modulation_enable_register);
case 0x1F801D92 - SPU_BASE:
return Truncate16(m_pitch_modulation_enable_register >> 16);
case 0x1F801D94 - SPU_BASE:
return Truncate16(m_noise_mode_register);
case 0x1F801D96 - SPU_BASE:
return Truncate16(m_noise_mode_register >> 16);
case 0x1F801D98 - SPU_BASE:
return Truncate16(m_reverb_on_register);
case 0x1F801D9A - SPU_BASE:
return Truncate16(m_reverb_on_register >> 16);
case 0x1F801D9C - SPU_BASE:
return Truncate16(m_endx_register);
case 0x1F801D9E - SPU_BASE:
return Truncate16(m_endx_register >> 16);
case 0x1F801DA2 - SPU_BASE:
return m_reverb_registers.mBASE;
case 0x1F801DA4 - SPU_BASE:
Log_TracePrintf("SPU IRQ address -> 0x%04X", ZeroExtend32(m_irq_address));
return m_irq_address;
case 0x1F801DA6 - SPU_BASE:
Log_TracePrintf("SPU transfer address register -> 0x%04X", ZeroExtend32(m_transfer_address_reg));
return m_transfer_address_reg;
case 0x1F801DA8 - SPU_BASE:
Log_TracePrintf("SPU transfer data register read");
return UINT16_C(0xFFFF);
case 0x1F801DAA - SPU_BASE:
Log_TracePrintf("SPU control register -> 0x%04X", ZeroExtend32(m_SPUCNT.bits));
return m_SPUCNT.bits;
case 0x1F801DAC - SPU_BASE:
Log_TracePrintf("SPU transfer control register -> 0x%04X", ZeroExtend32(m_transfer_control.bits));
return m_transfer_control.bits;
case 0x1F801DAE - SPU_BASE:
GeneratePendingSamples();
Log_TracePrintf("SPU status register -> 0x%04X", ZeroExtend32(m_SPUCNT.bits));
return m_SPUSTAT.bits;
case 0x1F801DB0 - SPU_BASE:
return m_cd_audio_volume_left;
case 0x1F801DB2 - SPU_BASE:
return m_cd_audio_volume_right;
case 0x1F801DB4 - SPU_BASE:
return m_external_volume_left;
case 0x1F801DB6 - SPU_BASE:
return m_external_volume_right;
case 0x1F801DB8 - SPU_BASE:
GeneratePendingSamples();
return m_main_volume_left.current_level;
case 0x1F801DBA - SPU_BASE:
GeneratePendingSamples();
return m_main_volume_right.current_level;
default:
{
if (offset < (0x1F801D80 - SPU_BASE))
return ReadVoiceRegister(offset);
if (offset >= (0x1F801DC0 - SPU_BASE) && offset < (0x1F801E00 - SPU_BASE))
return m_reverb_registers.rev[(offset - (0x1F801DC0 - SPU_BASE)) / 2];
if (offset >= (0x1F801E00 - SPU_BASE) && offset < (0x1F801E60 - SPU_BASE))
{
const u32 voice_index = (offset - (0x1F801E00 - SPU_BASE)) / 4;
GeneratePendingSamples();
if (offset & 0x02)
return m_voices[voice_index].left_volume.current_level;
else
return m_voices[voice_index].right_volume.current_level;
}
Log_DevPrintf("Unknown SPU register read: offset 0x%X (address 0x%08X)", offset, offset | SPU_BASE);
return UINT16_C(0xFFFF);
}
}
}
void SPU::WriteRegister(u32 offset, u16 value)
{
switch (offset)
{
case 0x1F801D80 - SPU_BASE:
{
Log_DebugPrintf("SPU main volume left <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_main_volume_left_reg.bits = value;
m_main_volume_left.Reset(m_main_volume_left_reg);
return;
}
case 0x1F801D82 - SPU_BASE:
{
Log_DebugPrintf("SPU main volume right <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_main_volume_right_reg.bits = value;
m_main_volume_right.Reset(m_main_volume_right_reg);
return;
}
case 0x1F801D84 - SPU_BASE:
{
Log_DebugPrintf("SPU reverb output volume left <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_reverb_registers.vLOUT = value;
return;
}
case 0x1F801D86 - SPU_BASE:
{
Log_DebugPrintf("SPU reverb output volume right <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_reverb_registers.vROUT = value;
return;
}
case 0x1F801D88 - SPU_BASE:
{
Log_DebugPrintf("SPU key on low <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_key_on_register = (m_key_on_register & 0xFFFF0000) | ZeroExtend32(value);
}
break;
case 0x1F801D8A - SPU_BASE:
{
Log_DebugPrintf("SPU key on high <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_key_on_register = (m_key_on_register & 0x0000FFFF) | (ZeroExtend32(value) << 16);
}
break;
case 0x1F801D8C - SPU_BASE:
{
Log_DebugPrintf("SPU key off low <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_key_off_register = (m_key_off_register & 0xFFFF0000) | ZeroExtend32(value);
}
break;
case 0x1F801D8E - SPU_BASE:
{
Log_DebugPrintf("SPU key off high <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_key_off_register = (m_key_off_register & 0x0000FFFF) | (ZeroExtend32(value) << 16);
}
break;
case 0x1F801D90 - SPU_BASE:
{
GeneratePendingSamples();
m_pitch_modulation_enable_register = (m_pitch_modulation_enable_register & 0xFFFF0000) | ZeroExtend32(value);
Log_DebugPrintf("SPU pitch modulation enable register <- 0x%08X", m_pitch_modulation_enable_register);
}
break;
case 0x1F801D92 - SPU_BASE:
{
GeneratePendingSamples();
m_pitch_modulation_enable_register =
(m_pitch_modulation_enable_register & 0x0000FFFF) | (ZeroExtend32(value) << 16);
Log_DebugPrintf("SPU pitch modulation enable register <- 0x%08X", m_pitch_modulation_enable_register);
}
break;
case 0x1F801D94 - SPU_BASE:
{
Log_DebugPrintf("SPU noise mode register <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_noise_mode_register = (m_noise_mode_register & 0xFFFF0000) | ZeroExtend32(value);
}
break;
case 0x1F801D96 - SPU_BASE:
{
Log_DebugPrintf("SPU noise mode register <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_noise_mode_register = (m_noise_mode_register & 0x0000FFFF) | (ZeroExtend32(value) << 16);
}
break;
case 0x1F801D98 - SPU_BASE:
{
Log_DebugPrintf("SPU reverb on register <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_reverb_on_register = (m_reverb_on_register & 0xFFFF0000) | ZeroExtend32(value);
}
break;
case 0x1F801D9A - SPU_BASE:
{
Log_DebugPrintf("SPU reverb on register <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_reverb_on_register = (m_reverb_on_register & 0x0000FFFF) | (ZeroExtend32(value) << 16);
}
break;
case 0x1F801DA2 - SPU_BASE:
{
Log_DebugPrintf("SPU reverb base address < 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_reverb_registers.mBASE = value;
m_reverb_base_address = ZeroExtend32(value << 2) & 0x3FFFFu;
m_reverb_current_address = m_reverb_base_address;
}
break;
case 0x1F801DA4 - SPU_BASE:
{
Log_DebugPrintf("SPU IRQ address register <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_irq_address = value;
if (IsRAMIRQTriggerable())
CheckForLateRAMIRQs();
return;
}
case 0x1F801DA6 - SPU_BASE:
{
Log_DebugPrintf("SPU transfer address register <- 0x%04X", ZeroExtend32(value));
m_transfer_event->InvokeEarly();
m_transfer_address_reg = value;
m_transfer_address = ZeroExtend32(value) * 8;
if (IsRAMIRQTriggerable() && CheckRAMIRQ(m_transfer_address))
{
Log_DebugPrintf("Trigger IRQ @ %08X %04X from transfer address reg set", m_transfer_address,
m_transfer_address / 8);
TriggerRAMIRQ();
}
return;
}
case 0x1F801DA8 - SPU_BASE:
{
Log_TracePrintf("SPU transfer data register <- 0x%04X (RAM offset 0x%08X)", ZeroExtend32(value),
m_transfer_address);
ManualTransferWrite(value);
return;
}
case 0x1F801DAA - SPU_BASE:
{
Log_DebugPrintf("SPU control register <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
const SPUCNT new_value{value};
if (new_value.ram_transfer_mode != m_SPUCNT.ram_transfer_mode &&
new_value.ram_transfer_mode == RAMTransferMode::Stopped)
{
// clear the fifo here?
if (!m_transfer_fifo.IsEmpty())
{
if (m_SPUCNT.ram_transfer_mode == RAMTransferMode::DMAWrite)
{
// I would guess on the console it would gradually write the FIFO out. Hopefully nothing relies on this
// level of timing granularity if we force it all out here.
Log_WarningPrintf("Draining write SPU transfer FIFO with %u bytes left", m_transfer_fifo.GetSize());
TickCount ticks = std::numeric_limits<TickCount>::max();
ExecuteFIFOWriteToRAM(ticks);
DebugAssert(m_transfer_fifo.IsEmpty());
}
else
{
Log_DebugPrintf("Clearing read SPU transfer FIFO with %u bytes left", m_transfer_fifo.GetSize());
m_transfer_fifo.Clear();
}
}
}
if (!new_value.enable && m_SPUCNT.enable)
{
// Mute all voices.
// Interestingly, hardware tests found this seems to happen immediately, not on the next 44100hz cycle.
for (u32 i = 0; i < NUM_VOICES; i++)
m_voices[i].ForceOff();
}
m_SPUCNT.bits = new_value.bits;
m_SPUSTAT.mode = m_SPUCNT.mode.GetValue();
if (!m_SPUCNT.irq9_enable)
m_SPUSTAT.irq9_flag = false;
else if (IsRAMIRQTriggerable())
CheckForLateRAMIRQs();
UpdateEventInterval();
UpdateDMARequest();
UpdateTransferEvent();
return;
}
case 0x1F801DAC - SPU_BASE:
{
Log_DebugPrintf("SPU transfer control register <- 0x%04X", ZeroExtend32(value));
m_transfer_control.bits = value;
return;
}
case 0x1F801DB0 - SPU_BASE:
{
Log_DebugPrintf("SPU left cd audio register <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_cd_audio_volume_left = value;
}
break;
case 0x1F801DB2 - SPU_BASE:
{
Log_DebugPrintf("SPU right cd audio register <- 0x%04X", ZeroExtend32(value));
GeneratePendingSamples();
m_cd_audio_volume_right = value;
}
break;
case 0x1F801DB4 - SPU_BASE:
{
// External volumes aren't used, so don't bother syncing.
Log_DebugPrintf("SPU left external volume register <- 0x%04X", ZeroExtend32(value));
m_external_volume_left = value;
}
break;
case 0x1F801DB6 - SPU_BASE:
{
// External volumes aren't used, so don't bother syncing.
Log_DebugPrintf("SPU right external volume register <- 0x%04X", ZeroExtend32(value));
m_external_volume_right = value;
}
break;
// read-only registers
case 0x1F801DAE - SPU_BASE:
{
return;
}
default:
{
if (offset < (0x1F801D80 - SPU_BASE))
{
WriteVoiceRegister(offset, value);
return;
}
if (offset >= (0x1F801DC0 - SPU_BASE) && offset < (0x1F801E00 - SPU_BASE))
{
const u32 reg = (offset - (0x1F801DC0 - SPU_BASE)) / 2;
Log_DebugPrintf("SPU reverb register %u <- 0x%04X", reg, value);
GeneratePendingSamples();
m_reverb_registers.rev[reg] = value;
return;
}
Log_DevPrintf("Unknown SPU register write: offset 0x%X (address 0x%08X) value 0x%04X", offset, offset | SPU_BASE,
ZeroExtend32(value));
return;
}
}
}
u16 SPU::ReadVoiceRegister(u32 offset)
{
const u32 reg_index = (offset % 0x10) / 2; //(offset & 0x0F) / 2;
const u32 voice_index = (offset / 0x10); //((offset >> 4) & 0x1F);
Assert(voice_index < 24);
// ADSR volume needs to be updated when reading. A voice might be off as well, but key on is pending.
const Voice& voice = m_voices[voice_index];
if (reg_index >= 6 && (voice.IsOn() || m_key_on_register & (1u << voice_index)))
GeneratePendingSamples();
Log_TracePrintf("Read voice %u register %u -> 0x%02X", voice_index, reg_index, voice.regs.index[reg_index]);
return voice.regs.index[reg_index];
}
void SPU::WriteVoiceRegister(u32 offset, u16 value)
{
// per-voice registers
const u32 reg_index = (offset % 0x10);
const u32 voice_index = (offset / 0x10);
DebugAssert(voice_index < 24);
Voice& voice = m_voices[voice_index];
if (voice.IsOn() || m_key_on_register & (1u << voice_index))
GeneratePendingSamples();
switch (reg_index)
{
case 0x00: // volume left
{
Log_DebugPrintf("SPU voice %u volume left <- 0x%04X", voice_index, value);
voice.regs.volume_left.bits = value;
voice.left_volume.Reset(voice.regs.volume_left);
}
break;
case 0x02: // volume right
{
Log_DebugPrintf("SPU voice %u volume right <- 0x%04X", voice_index, value);
voice.regs.volume_right.bits = value;
voice.right_volume.Reset(voice.regs.volume_right);
}
break;
case 0x04: // sample rate
{
Log_DebugPrintf("SPU voice %u ADPCM sample rate <- 0x%04X", voice_index, value);
voice.regs.adpcm_sample_rate = value;
}
break;
case 0x06: // start address
{
Log_DebugPrintf("SPU voice %u ADPCM start address <- 0x%04X", voice_index, value);
voice.regs.adpcm_start_address = value;
}
break;
case 0x08: // adsr low
{
Log_DebugPrintf("SPU voice %u ADSR low <- 0x%04X (was 0x%04X)", voice_index, value, voice.regs.adsr.bits_low);
voice.regs.adsr.bits_low = value;
if (voice.IsOn())
voice.UpdateADSREnvelope();
}
break;
case 0x0A: // adsr high
{
Log_DebugPrintf("SPU voice %u ADSR high <- 0x%04X (was 0x%04X)", voice_index, value, voice.regs.adsr.bits_low);
voice.regs.adsr.bits_high = value;
if (voice.IsOn())
voice.UpdateADSREnvelope();
}
break;
case 0x0C: // adsr volume
{
Log_DebugPrintf("SPU voice %u ADSR volume <- 0x%04X (was 0x%04X)", voice_index, value, voice.regs.adsr_volume);
voice.regs.adsr_volume = value;
}
break;
case 0x0E: // repeat address
{
// There is a short window of time here between the voice being keyed on and the first block finishing decoding
// where setting the repeat address will *NOT* ignore the block/loop start flag. Games sensitive to this are:
// - The Misadventures of Tron Bonne
// - Re-Loaded - The Hardcore Sequel
// - Valkyrie Profile
const bool ignore_loop_address = voice.IsOn() && !voice.is_first_block;
Log_DebugPrintf("SPU voice %u ADPCM repeat address <- 0x%04X", voice_index, value);
voice.regs.adpcm_repeat_address = value;
voice.ignore_loop_address |= ignore_loop_address;
if (!ignore_loop_address)
{
Log_DevPrintf("Not ignoring loop address, the ADPCM repeat address of 0x%04X for voice %u will be overwritten",
value, voice_index);
}
}
break;
default:
{
Log_ErrorPrintf("Unknown SPU voice %u register write: offset 0x%X (address 0x%08X) value 0x%04X", offset,
voice_index, offset | SPU_BASE, ZeroExtend32(value));
}
break;
}
}
void SPU::TriggerRAMIRQ()
{
DebugAssert(IsRAMIRQTriggerable());
m_SPUSTAT.irq9_flag = true;
g_interrupt_controller.InterruptRequest(InterruptController::IRQ::SPU);
}
void SPU::CheckForLateRAMIRQs()
{
if (CheckRAMIRQ(m_transfer_address))
{
Log_DebugPrintf("Trigger IRQ @ %08X %04X from late transfer", m_transfer_address, m_transfer_address / 8);
TriggerRAMIRQ();
return;
}
for (u32 i = 0; i < NUM_VOICES; i++)
{
// we skip voices which haven't started this block yet - because they'll check
// the next time they're sampled, and the delay might be important.
const Voice& v = m_voices[i];
if (!v.has_samples)
continue;
const u32 address = v.current_address * 8;
if (CheckRAMIRQ(address) || CheckRAMIRQ((address + 8) & RAM_MASK))
{
Log_DebugPrintf("Trigger IRQ @ %08X %04X from late", address, address / 8);
TriggerRAMIRQ();
return;
}
}
}
void SPU::WriteToCaptureBuffer(u32 index, s16 value)
{
const u32 ram_address = (index * CAPTURE_BUFFER_SIZE_PER_CHANNEL) | ZeroExtend16(m_capture_buffer_position);
// Log_DebugPrintf("write to capture buffer %u (0x%08X) <- 0x%04X", index, ram_address, u16(value));
std::memcpy(&m_ram[ram_address], &value, sizeof(value));
if (IsRAMIRQTriggerable() && CheckRAMIRQ(ram_address))
{
Log_DebugPrintf("Trigger IRQ @ %08X %04X from capture buffer", ram_address, ram_address / 8);
TriggerRAMIRQ();
}
}
void SPU::IncrementCaptureBufferPosition()
{
m_capture_buffer_position += sizeof(s16);
m_capture_buffer_position %= CAPTURE_BUFFER_SIZE_PER_CHANNEL;
m_SPUSTAT.second_half_capture_buffer = m_capture_buffer_position >= (CAPTURE_BUFFER_SIZE_PER_CHANNEL / 2);
}
void ALWAYS_INLINE SPU::ExecuteFIFOReadFromRAM(TickCount& ticks)
{
while (ticks > 0 && !m_transfer_fifo.IsFull())
{
u16 value;
std::memcpy(&value, &m_ram[m_transfer_address], sizeof(u16));
m_transfer_address = (m_transfer_address + sizeof(u16)) & RAM_MASK;
m_transfer_fifo.Push(value);
ticks -= TRANSFER_TICKS_PER_HALFWORD;
if (IsRAMIRQTriggerable() && CheckRAMIRQ(m_transfer_address))
{
Log_DebugPrintf("Trigger IRQ @ %08X %04X from transfer read", m_transfer_address, m_transfer_address / 8);
TriggerRAMIRQ();
}
}
}
void ALWAYS_INLINE SPU::ExecuteFIFOWriteToRAM(TickCount& ticks)
{
while (ticks > 0 && !m_transfer_fifo.IsEmpty())
{
u16 value = m_transfer_fifo.Pop();
std::memcpy(&m_ram[m_transfer_address], &value, sizeof(u16));
m_transfer_address = (m_transfer_address + sizeof(u16)) & RAM_MASK;
ticks -= TRANSFER_TICKS_PER_HALFWORD;
if (IsRAMIRQTriggerable() && CheckRAMIRQ(m_transfer_address))
{
Log_DebugPrintf("Trigger IRQ @ %08X %04X from transfer write", m_transfer_address, m_transfer_address / 8);
TriggerRAMIRQ();
}
}
}
void SPU::ExecuteTransfer(TickCount ticks)
{
const RAMTransferMode mode = m_SPUCNT.ram_transfer_mode;
Assert(mode != RAMTransferMode::Stopped);
if (mode == RAMTransferMode::DMARead)
{
while (ticks > 0 && !m_transfer_fifo.IsFull())
{
ExecuteFIFOReadFromRAM(ticks);
// this can result in the FIFO being emptied, hence double the while loop
UpdateDMARequest();
}
// we're done if we have no more data to read
if (m_transfer_fifo.IsFull())
{
m_SPUSTAT.transfer_busy = false;
m_transfer_event->Deactivate();
return;
}
m_SPUSTAT.transfer_busy = true;
const TickCount ticks_until_complete =
TickCount(m_transfer_fifo.GetSpace() * u32(TRANSFER_TICKS_PER_HALFWORD)) + ((ticks < 0) ? -ticks : 0);
m_transfer_event->Schedule(ticks_until_complete);
}
else
{
// write the fifo to ram, request dma again when empty
while (ticks > 0 && !m_transfer_fifo.IsEmpty())
{
ExecuteFIFOWriteToRAM(ticks);
// similar deal here, the FIFO can be written out in a long slice
UpdateDMARequest();
}
// we're done if we have no more data to write
if (m_transfer_fifo.IsEmpty())
{
m_SPUSTAT.transfer_busy = false;
m_transfer_event->Deactivate();
return;
}
m_SPUSTAT.transfer_busy = true;
const TickCount ticks_until_complete =
TickCount(m_transfer_fifo.GetSize() * u32(TRANSFER_TICKS_PER_HALFWORD)) + ((ticks < 0) ? -ticks : 0);
m_transfer_event->Schedule(ticks_until_complete);
}
}
void SPU::ManualTransferWrite(u16 value)
{
if (m_transfer_fifo.IsFull())
{
Log_WarningPrintf("FIFO full, dropping write of 0x%04X", value);
return;
}
m_transfer_fifo.Push(value);
UpdateTransferEvent();
}
void SPU::UpdateTransferEvent()
{
const RAMTransferMode mode = m_SPUCNT.ram_transfer_mode;
if (mode == RAMTransferMode::Stopped)
{
m_transfer_event->Deactivate();
}
else if (mode == RAMTransferMode::DMARead)
{
// transfer event fills the fifo
if (m_transfer_fifo.IsFull())
m_transfer_event->Deactivate();
else if (!m_transfer_event->IsActive())
m_transfer_event->Schedule(TickCount(m_transfer_fifo.GetSpace() * u32(TRANSFER_TICKS_PER_HALFWORD)));
}
else
{
// transfer event copies from fifo to ram
if (m_transfer_fifo.IsEmpty())
m_transfer_event->Deactivate();
else if (!m_transfer_event->IsActive())
m_transfer_event->Schedule(TickCount(m_transfer_fifo.GetSize() * u32(TRANSFER_TICKS_PER_HALFWORD)));
}
m_SPUSTAT.transfer_busy = m_transfer_event->IsActive();
}
void SPU::UpdateDMARequest()
{
switch (m_SPUCNT.ram_transfer_mode)
{
case RAMTransferMode::DMARead:
m_SPUSTAT.dma_read_request = m_transfer_fifo.IsFull();
m_SPUSTAT.dma_write_request = false;
m_SPUSTAT.dma_request = m_SPUSTAT.dma_read_request;
break;
case RAMTransferMode::DMAWrite:
m_SPUSTAT.dma_read_request = false;
m_SPUSTAT.dma_write_request = m_transfer_fifo.IsEmpty();
m_SPUSTAT.dma_request = m_SPUSTAT.dma_write_request;
break;
case RAMTransferMode::Stopped:
case RAMTransferMode::ManualWrite:
default:
m_SPUSTAT.dma_read_request = false;
m_SPUSTAT.dma_write_request = false;
m_SPUSTAT.dma_request = false;
break;
}
// This might call us back directly.
g_dma.SetRequest(DMA::Channel::SPU, m_SPUSTAT.dma_request);
}
void SPU::DMARead(u32* words, u32 word_count)
{
/*
From @JaCzekanski - behavior when block size is larger than the FIFO size
for blocks <= 0x16 - all data is transferred correctly
using block size 0x20 transfer behaves strange:
% Writing 524288 bytes to SPU RAM to 0x00000000 using DMA... ok
% Reading 256 bytes from SPU RAM from 0x00001000 using DMA... ok
% 0x00001000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ................
% 0x00001010: 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f ................
% 0x00001020: 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f !"#$%&'()*+,-./
% 0x00001030: 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 0123456789:;<=>?
% 0x00001040: 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f >?>?>?>?>?>?>?>?
% 0x00001050: 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f >?>?>?>?>?>?>?>?
% 0x00001060: 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f >?>?>?>?>?>?>?>?
% 0x00001070: 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f 3e 3f >?>?>?>?>?>?>?>?
% 0x00001080: 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO
% 0x00001090: 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f PQRSTUVWXYZ[\]^_
% 0x000010a0: 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f `abcdefghijklmno
% 0x000010b0: 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f pqrstuvwxyz{|}~.
% 0x000010c0: 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f ~.~.~.~.~.~.~.~.
% 0x000010d0: 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f ~.~.~.~.~.~.~.~.
% 0x000010e0: 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f ~.~.~.~.~.~.~.~.
% 0x000010f0: 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f 7e 7f ~.~.~.~.~.~.~.~.
Using Block size = 0x10 (correct data)
% Reading 256 bytes from SPU RAM from 0x00001000 using DMA... ok
% 0x00001000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ................
% 0x00001010: 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f ................
% 0x00001020: 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f !"#$%&'()*+,-./
% 0x00001030: 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 0123456789:;<=>?
% 0x00001040: 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO
% 0x00001050: 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f PQRSTUVWXYZ[\]^_
% 0x00001060: 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f `abcdefghijklmno
% 0x00001070: 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f pqrstuvwxyz{|}~.
% 0x00001080: 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f ................
% 0x00001090: 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f ................
% 0x000010a0: a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af ................
% 0x000010b0: b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf ................
% 0x000010c0: c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf ................
% 0x000010d0: d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df ................
% 0x000010e0: e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef ................
% 0x000010f0: f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff ................
*/
u16* halfwords = reinterpret_cast<u16*>(words);
u32 halfword_count = word_count * 2;
const u32 size = m_transfer_fifo.GetSize();
if (word_count > size)
{
u16 fill_value = 0;
if (size > 0)
{
m_transfer_fifo.PopRange(halfwords, size);
fill_value = halfwords[size - 1];
}
Log_WarningPrintf("Transfer FIFO underflow, filling with 0x%04X", fill_value);
std::fill_n(&halfwords[size], halfword_count - size, fill_value);
}
else
{
m_transfer_fifo.PopRange(halfwords, halfword_count);
}
UpdateDMARequest();
UpdateTransferEvent();
}
void SPU::DMAWrite(const u32* words, u32 word_count)
{
const u16* halfwords = reinterpret_cast<const u16*>(words);
u32 halfword_count = word_count * 2;
const u32 words_to_transfer = std::min(m_transfer_fifo.GetSpace(), halfword_count);
m_transfer_fifo.PushRange(halfwords, words_to_transfer);
if (words_to_transfer != halfword_count)
Log_WarningPrintf("Transfer FIFO overflow, dropping %u halfwords", halfword_count - words_to_transfer);
UpdateDMARequest();
UpdateTransferEvent();
}
void SPU::GeneratePendingSamples()
{