Carry Verilog 2001 attributes with processes,

 all the way through to the ivl_target API.

 Divide signal reference counts between rval
 and lval references.

Attrib.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: Attrib.cc,v 1.3 2002/05/23 03:08:50 steve Exp $"
+#ident "$Id: Attrib.cc,v 1.4 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -103,18 +103,18 @@ bool Attrib::has_compat_attributes(const Attrib&that) const
       return true;
 }
 
-unsigned Attrib::size() const
+unsigned Attrib::attr_cnt() const
 {
       return nlist_;
 }
 
-string Attrib::key(unsigned idx) const
+const char* Attrib::attr_key(unsigned idx) const
 {
       assert(idx < nlist_);
-      return list_[idx].key;
+      return list_[idx].key.c_str();
 }
 
-const verinum& Attrib::value(unsigned idx) const
+const verinum& Attrib::attr_value(unsigned idx) const
 {
       assert(idx < nlist_);
       return list_[idx].val;
@@ -123,6 +123,13 @@ const verinum& Attrib::value(unsigned idx) const
 
 /*
  * $Log: Attrib.cc,v $
+ * Revision 1.4  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.3  2002/05/23 03:08:50  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

Attrib.h

@@ -19,11 +19,10 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: Attrib.h,v 1.2 2002/05/23 03:08:50 steve Exp $"
+#ident "$Id: Attrib.h,v 1.3 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include  <string>
-# include  <map>
 # include  "verinum.h"
 
 /*
@@ -42,9 +41,9 @@ class Attrib {
 
 
 	/* Provide a means of iterating over the entries in the map. */
-      unsigned size() const;
-      string key(unsigned idx) const;
-      const verinum& value(unsigned idx) const;
+      unsigned       attr_cnt() const;
+      const char*    attr_key(unsigned idx) const;
+      const verinum& attr_value(unsigned idx) const;
 
 
     private:
@@ -63,6 +62,13 @@ class Attrib {
 
 /*
  * $Log: Attrib.h,v $
+ * Revision 1.3  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.2  2002/05/23 03:08:50  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

Statement.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Statement.h,v 1.33 2002/04/21 22:31:02 steve Exp $"
+#ident "$Id: Statement.h,v 1.34 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include  <string>
@@ -56,6 +56,8 @@ class PProcess : public LineInfo {
       Type type() const { return type_; }
       Statement*statement() { return statement_; }
 
+      map<string,PExpr*> attributes;
+
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -453,6 +455,13 @@ class PWhile  : public Statement {
 
 /*
  * $Log: Statement.h,v $
+ * Revision 1.34  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.33  2002/04/21 22:31:02  steve
  *  Redo handling of assignment internal delays.
  *  Leave it possible for them to be calculated

cprop.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: cprop.cc,v 1.34 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: cprop.cc,v 1.35 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -915,7 +915,7 @@ void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)
 		    // If the net has an eref, then there is an
 		    // expression somewhere that reads this signal. So
 		    // the constant does get read.
-		  if (tmp->get_eref() > 0)
+		  if (tmp->peek_eref() > 0)
 			return;
 
 		    // If the net is a port of the root module, then
@@ -949,6 +949,13 @@ void cprop(Design*des)
 
 /*
  * $Log: cprop.cc,v $
+ * Revision 1.35  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.34  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

design_dump.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: design_dump.cc,v 1.123 2002/05/05 21:11:49 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.124 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -93,7 +93,7 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
 	    o << " inout";
 	    break;
       }
-      o << " (eref=" << get_eref() << ")";
+      o << " (eref=" << peek_eref() << ", lref=" << peek_lref() << ")";
       if (scope())
 	    o << " scope=" << scope()->name();
       o << " #(" << rise_time() << "," << fall_time() << "," <<
@@ -174,9 +174,9 @@ void NetObj::dump_node_pins(ostream&o, unsigned ind) const
 void NetObj::dump_obj_attr(ostream&o, unsigned ind) const
 {
       unsigned idx;
-      for (idx = 0 ;  idx < attributes_.size() ;  idx += 1) {
-	    o << setw(ind) << "" << attributes_.key(idx) << " = \"" <<
-		  attributes_.value(idx) << "\"" << endl;
+      for (idx = 0 ;  idx < attr_cnt() ;  idx += 1) {
+	    o << setw(ind) << "" << attr_key(idx) << " = \"" <<
+		  attr_value(idx) << "\"" << endl;
       }
 }
 
@@ -413,6 +413,11 @@ void NetProcTop::dump(ostream&o, unsigned ind) const
 	    break;
       }
 
+      for (unsigned idx = 0 ;  idx < attr_cnt() ;  idx += 1) {
+	    o << setw(ind+2) << "" << "(* " << attr_key(idx) << " = "
+	      << attr_value(idx) << " *)" << endl;
+      }
+
       statement_->dump(o, ind+2);
 }
 
@@ -980,6 +985,13 @@ void Design::dump(ostream&o) const
 
 /*
  * $Log: design_dump.cc,v $
+ * Revision 1.124  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.123  2002/05/05 21:11:49  steve
  *  Put off evaluation of concatenation repeat expresions
  *  until after parameters are defined. This allows parms

elaborate.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elaborate.cc,v 1.249 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.250 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -2417,7 +2417,9 @@ bool Module::elaborate(Design*des, NetScope*scope) const
 	    (*gt)->elaborate(des, scope);
       }
 
-	// Elaborate the behaviors, making processes out of them.
+	// Elaborate the behaviors, making processes out of them. This
+	// involves scanning the PProcess* list, creating a NetProcTop
+	// for each process.
       const list<PProcess*>&sl = get_behaviors();
 
       for (list<PProcess*>::const_iterator st = sl.begin()
@@ -2440,6 +2442,21 @@ bool Module::elaborate(Design*des, NetScope*scope) const
 		  break;
 	    }
 
+	      // Evaluate the attributes for this process, if there
+	      // are any. These attributes are to be attached to the
+	      // NetProcTop object.
+	    struct attrib_list_t*attrib_list = 0;
+	    unsigned attrib_list_n = 0;
+	    attrib_list = evaluate_attributes((*st)->attributes,
+					      attrib_list_n,
+					      des, scope);
+
+	    for (unsigned adx = 0 ;  adx < attrib_list_n ;  adx += 1)
+		  top->attribute(attrib_list[adx].key,
+				 attrib_list[adx].val);
+
+	    delete[]attrib_list;
+
 	    top->set_line(*(*st));
 	    des->add_process(top);
       }
@@ -2551,6 +2568,13 @@ Design* elaborate(list<const char*>roots)
 
 /*
  * $Log: elaborate.cc,v $
+ * Revision 1.250  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.249  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

expr_synth.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: expr_synth.cc,v 1.32 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: expr_synth.cc,v 1.33 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -378,7 +378,7 @@ NetNet* NetEConcat::synthesize(Design*des)
 		  obit += 1;
 	    }
 
-	    if (tmp[idx-1]->local_flag() && tmp[idx-1]->get_eref() == 0)
+	    if (tmp[idx-1]->local_flag() && tmp[idx-1]->get_refs() == 0)
 		  delete tmp[idx-1];
       }
 
@@ -587,6 +587,13 @@ NetNet* NetESignal::synthesize(Design*des)
 
 /*
  * $Log: expr_synth.cc,v $
+ * Revision 1.33  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.32  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

ivl.def

@@ -131,6 +131,8 @@ ivl_signal_type
 ivl_signal_name
 ivl_signal_basename
 
+ivl_process_attr_cnt
+ivl_process_attr_val
 ivl_process_scope
 ivl_process_stmt
 ivl_process_type

ivl_target.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: ivl_target.h,v 1.96 2002/05/24 04:36:23 steve Exp $"
+#ident "$Id: ivl_target.h,v 1.97 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 #ifdef __cplusplus
@@ -938,13 +938,19 @@ extern ivl_attribute_t ivl_signal_attr_val(ivl_signal_t net, unsigned idx);
  * The ivl_process_stmt function gets the statement that forms the
  * process. See the statement related functions for how to manipulate
  * statements.
+ *
+ * Processes can have attributes attached to them. the attr_cnt and
+ * attr_val methods return those attributes.
  */
 extern ivl_process_type_t ivl_process_type(ivl_process_t net);
 
 extern ivl_scope_t ivl_process_scope(ivl_process_t net);
 
 extern ivl_statement_t ivl_process_stmt(ivl_process_t net);
 
+extern unsigned        ivl_process_attr_cnt(ivl_process_t net);
+extern ivl_attribute_t ivl_process_attr_val(ivl_process_t net, unsigned idx);
+
 /*
  * These functions manage statements of various type. This includes
  * all the different kinds of statements (as enumerated in
@@ -1037,6 +1043,13 @@ _END_DECL
 
 /*
  * $Log: ivl_target.h,v $
+ * Revision 1.97  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.96  2002/05/24 04:36:23  steve
  *  Verilog 2001 attriubtes on nets/wires.
  *

net_assign.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: net_assign.cc,v 1.9 2002/04/21 22:31:02 steve Exp $"
+#ident "$Id: net_assign.cc,v 1.10 2002/05/26 01:39:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -43,13 +43,13 @@ NetAssign_::NetAssign_(NetNet*s)
 {
       loff_ = 0;
       lwid_ = sig_->pin_count();
-      sig_->incr_eref();
+      sig_->incr_lref();
       more = 0;
 }
 
 NetAssign_::~NetAssign_()
 {
-      if (sig_) sig_->decr_eref();
+      if (sig_) sig_->decr_lref();
       assert( more == 0 );
       if (bmux_) delete bmux_;
 }
@@ -210,6 +210,13 @@ NetAssignNB::~NetAssignNB()
 
 /*
  * $Log: net_assign.cc,v $
+ * Revision 1.10  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
  * Revision 1.9  2002/04/21 22:31:02  steve
  *  Redo handling of assignment internal delays.
  *  Leave it possible for them to be calculated