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Add zero replication tests
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@caryr
caryr committed Aug 18, 2015
1 parent 49452dc commit 4b2ed1a
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Showing 10 changed files with 64 additions and 8 deletions.
2 changes: 1 addition & 1 deletion gold/indef_width_concat-v0.9.gold
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@@ -1,4 +1,4 @@
./ivltests/indef_width_concat.v:4: error: Concatenation operand "pval" has indefinite width.
./ivltests/indef_width_concat.v:4: error: Concatenation operand "'sd2" has indefinite width.
./ivltests/indef_width_concat.v:4: error: Concatenation may not have zero width in this context.
./ivltests/indef_width_concat.v:4: error: Concatenation/replication may not have zero width in this context.
3 error(s) during elaboration.
5 changes: 3 additions & 2 deletions gold/real_invalid_ops-v0.9.gold
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Expand Up @@ -39,7 +39,7 @@
./ivltests/real_invalid_ops.v:28: error: >>> operator may not have REAL operands.
./ivltests/real_invalid_ops.v:28: error: Unable to elaborate r-value: (var1)>>>(var2)
./ivltests/real_invalid_ops.v:30: error: Concatenation operand can not be real: var1
./ivltests/real_invalid_ops.v:30: error: Concatenation may not have zero width in this context.
./ivltests/real_invalid_ops.v:30: error: Concatenation/replication may not have zero width in this context.
./ivltests/real_invalid_ops.v:30: error: Unable to elaborate r-value: {var1}
./ivltests/real_invalid_ops.v:31: error: Concatenation repeat expression can not be REAL.
./ivltests/real_invalid_ops.v:31: error: Unable to elaborate r-value: {2.00000{var1}}
Expand All @@ -64,5 +64,6 @@
./ivltests/real_invalid_ops.v:61: error: >> operator may not have REAL operands.
./ivltests/real_invalid_ops.v:62: error: >>> operator may not have REAL operands.
./ivltests/real_invalid_ops.v:64: error: Concatenation operand can not be real: var1
./ivltests/real_invalid_ops.v:64: error: Concatenation/replication may not have zero width in this context.
./ivltests/real_invalid_ops.v:65: error: Concatenation repeat expression can not be REAL.
67 error(s) during elaboration.
68 error(s) during elaboration.
31 changes: 31 additions & 0 deletions ivltests/zero_repl.v
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@@ -0,0 +1,31 @@
module test;
parameter width = 32;
localparam fill = 32 - width;
localparam extend = 0;

reg passed;
reg [width-1:0] in;
reg [31:0] lat1, lat2;
wire sign_bit = in[width-1];
wire lsb = in[0];

initial begin
passed = 1'b1;
in = 32'h80000001;
// The following are asserting().
lat1 <= {{fill{sign_bit}}, in, {extend{lsb}}};
lat2 = {{fill{sign_bit}}, in, {extend{lsb}}};
#1;
if (lat1 !== 32'h80000001) begin
$display("FAILED: zero-replication (NB): got %h", lat1);
passed = 1'b0;
end
if (lat2 !== 32'h80000001) begin
$display("FAILED: zero-replication (B): got %h", lat2);
passed = 1'b0;
end

if (passed) $display("PASSED");
end

endmodule
12 changes: 12 additions & 0 deletions ivltests/zero_repl_fail.v
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@@ -0,0 +1,12 @@
module test;
reg [31:0] lat;
wire sign_bit = 1'b1;

initial begin
// This should be reported as a syntax error (replicating a zero width).
lat = {{2{{0{sign_bit}}}}, 16'h0001};

$display("FAILED");
end

endmodule
2 changes: 2 additions & 0 deletions regress-vlg.list
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Expand Up @@ -1608,3 +1608,5 @@ writememh2 normal ivltests # pr#400
xnor_test normal ivltests # ~^ in an IF()
z1 normal ivltests foo
z2 normal ivltests foo
zero_repl normal ivltests
zero_repl_fail CE ivltests
4 changes: 3 additions & 1 deletion regression_report-devel.txt
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Expand Up @@ -1717,6 +1717,8 @@ test_mos_strength_reduction: Passed.
xnor_test: Passed.
z1: Passed.
z2: Passed.
zero_repl: Passed.
zero_repl_fail: Passed - CE.
analog1: ==> Failed - running iverilog.
analog2: ==> Failed - running iverilog.
cast_int: Passed.
Expand Down Expand Up @@ -2162,4 +2164,4 @@ test_mos_strength_reduction: Passed.
ufuncsynth1: Passed.
============================================================================
Test results:
Total=2160, Passed=2154, Failed=6, Not Implemented=0, Expected Fail=0
Total=2162, Passed=2156, Failed=6, Not Implemented=0, Expected Fail=0
4 changes: 3 additions & 1 deletion regression_report-strict.txt
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Expand Up @@ -1714,6 +1714,8 @@ test_mos_strength_reduction: Passed.
xnor_test: Passed.
z1: Passed.
z2: Passed.
zero_repl: Passed.
zero_repl_fail: Passed - CE.
analog1: ==> Failed - running iverilog.
analog2: ==> Failed - running iverilog.
cast_int: Passed.
Expand Down Expand Up @@ -2159,4 +2161,4 @@ test_mos_strength_reduction: Passed.
ufuncsynth1: Passed.
============================================================================
Test results:
Total=2157, Passed=2151, Failed=6, Not Implemented=0, Expected Fail=0
Total=2159, Passed=2153, Failed=6, Not Implemented=0, Expected Fail=0
4 changes: 3 additions & 1 deletion regression_report-v0.9.txt
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Expand Up @@ -1696,6 +1696,8 @@ test_mos_strength_reduction: Passed.
xnor_test: Passed.
z1: Passed.
z2: Passed.
zero_repl: Passed.
zero_repl_fail: Passed - CE.
cast_int: Passed.
scaled_real: Passed.
test_vams_math: Passed.
Expand Down Expand Up @@ -1777,4 +1779,4 @@ test_mos_strength_reduction: Passed.
ufuncsynth1: Passed.
============================================================================
Test results:
Total=1775, Passed=1644, Failed=0, Not Implemented=74, Expected Fail=57
Total=1777, Passed=1646, Failed=0, Not Implemented=74, Expected Fail=57
4 changes: 3 additions & 1 deletion regression_report-v10.txt
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Expand Up @@ -1719,6 +1719,8 @@ test_mos_strength_reduction: Passed.
xnor_test: Passed.
z1: Passed.
z2: Passed.
zero_repl: Passed.
zero_repl_fail: Passed - CE.
cast_int: Passed.
constfunc4: Passed.
scaled_real: Passed.
Expand Down Expand Up @@ -2162,4 +2164,4 @@ test_mos_strength_reduction: Passed.
ufuncsynth1: Passed.
============================================================================
Test results:
Total=2160, Passed=2154, Failed=4, Not Implemented=2, Expected Fail=0
Total=2162, Passed=2156, Failed=4, Not Implemented=2, Expected Fail=0
4 changes: 3 additions & 1 deletion regression_report-vlog95.txt
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Expand Up @@ -1953,6 +1953,8 @@ test_mos_strength_reduction: Passed.
xnor_test: Passed.
z1: Passed.
z2: Passed.
zero_repl: Passed.
zero_repl_fail: Passed - CE.
scaled_real: Passed.
test_vams_math: Passed.
value_range1: Passed.
Expand Down Expand Up @@ -2162,4 +2164,4 @@ test_mos_strength_reduction: Passed.
synth_if_no_else: Passed.
============================================================================
Test results:
Total=2160, Passed=2129, Failed=4, Not Implemented=3, Expected Fail=24
Total=2162, Passed=2131, Failed=4, Not Implemented=3, Expected Fail=24

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