Updated test lists and expected results for latch synthesis.

gold/casesynth7.gold

@@ -0,0 +1,2 @@
+./ivltests/casesynth7.v:16: warning: A latch has been inferred for 'o'.
+./ivltests/casesynth7.v:16: warning: The latch enable is connected to a synthesized expression. The latch may be sensitive to glitches.

ivltests/casesynth7.v

@@ -1,7 +1,7 @@
-// We don't support incomplete case statements in asynchronous logic synthesis.
-// Such constructs are dangerous in synthesisable code, as in real hardware
-// the inferred latch will be sensitive to glitches as the case select value
-// changes. Check that the compiler correctly rejects this code.
+// Incomplete case statements in asynchronous logic are dangerous in
+// synthesisable code, as in real hardware the inferred latch will be
+// sensitive to glitches as the case select value changes. Check that
+// the compiler outputs a warning for this.
 module mux(
 
 input wire [2:0] sel,

regress-synth.list

@@ -65,6 +65,11 @@
 # gold or diff commands.
 #
 
+# We no longer support the ivl_full_case attribute. This is a dangerous
+# thing to use, as it results in synthesis vs. simulation mismatches.
+#full_case		normal			ivltests
+#full_case2		normal			ivltests
+
 basicexpr		normal			ivltests
 basicexpr2		normal			ivltests
 basicexpr3		normal			ivltests
@@ -95,7 +100,7 @@ casesynth3		normal			ivltests
 casesynth4		normal			ivltests
 casesynth5		normal			ivltests
 casesynth6		normal			ivltests
-casesynth7		CE			ivltests
+casesynth7		normal			ivltests gold=casesynth7.gold
 casesynth8		CE			ivltests
 casesynth9		normal			ivltests
 casex_synth		normal			ivltests
@@ -117,8 +122,6 @@ dffsynth11		normal			ivltests
 ff_dual_enable		normal			ivltests
 for_loop_synth		normal			ivltests
 for_loop_synth2		normal			ivltests
-full_case		normal			ivltests
-full_case2		normal			ivltests
 if_part_no_else		normal			ivltests
 if_part_no_else2	normal			ivltests
 inside_synth		normal			ivltests

regress-v10.list

@@ -1,5 +1,5 @@
 # This test list is used to override other test lists when using
-# Icarus Verilog v0.10.
+# Icarus Verilog v10.
 
 #
 # Copyright (c) 1999-2015 Guy Hutchison (ghutchis@pacbell.net)
@@ -99,6 +99,7 @@ case6			normal			ivltests
 casesynth1		normal			ivltests
 casesynth2		normal			ivltests
 casesynth3		normal			ivltests
+casesynth7		NI
 casex_synth		normal			ivltests
 condit1			normal			ivltests
 conditsynth1		normal			ivltests
@@ -110,8 +111,6 @@ dffsynth4		normal			ivltests
 dffsynth9		normal			ivltests
 dffsynth10		normal			ivltests
 dffsynth11		normal			ivltests
-full_case		normal			ivltests
-full_case2		normal			ivltests
 inside_synth		normal			ivltests
 inside_synth3		normal			ivltests
 memsynth1		normal			ivltests

regress-v11.list

@@ -1,5 +1,5 @@
 # This test list is used to override other test lists when using
-# Icarus Verilog v0.10.
+# Icarus Verilog v11.
 
 #
 # Copyright (c) 1999-2015 Guy Hutchison (ghutchis@pacbell.net)
@@ -65,15 +65,7 @@
 #
 
 # v11 has incomplete synthesis support
-basiclatch		CE,-S			ivltests
-case1			CE,-S			ivltests
-case2			CE,-S			ivltests
-casex_synth		CE,-S			ivltests
 dffsynth		CE,-S			ivltests
-full_case		CE,-S			ivltests
-full_case2		CE,-S			ivltests
-inside_synth		CE,-S			ivltests
-inside_synth3		CE,-S			ivltests
 memsynth1		CE,-S			ivltests
 memsynth2		CE,-S			ivltests
 memsynth3		CE,-S			ivltests
@@ -82,3 +74,8 @@ memsynth6		CE,-S			ivltests
 memsynth7		CE,-S			ivltests
 memsynth9		CE,-S			ivltests
 mix_reset		CE,-S			ivltests
+
+# These tests pass, but synthesis is creating unnecessary latches.
+case1			normal			ivltests
+case2			normal			ivltests
+casex_synth		normal			ivltests

regress-vlog95.list

@@ -480,6 +480,7 @@ br994			TE,-S			ivltests
 casesynth1		TE,-S			ivltests
 casesynth2		TE,-S			ivltests
 casesynth3		TE,-S			ivltests
+casesynth7		TE,-S			ivltests
 conditsynth1		TE,-S			ivltests
 conditsynth2		TE,-S			ivltests
 conditsynth3		TE,-S			ivltests

regression_report-devel.txt

@@ -1,14 +1,6 @@
 Running compiler/VVP tests for Icarus Verilog version: 11.
 ----------------------------------------------------------------------------
-                 basiclatch: Passed - CE.
-                      case1: Passed - CE.
-                      case2: Passed - CE.
-                casex_synth: Passed - CE.
                    dffsynth: Passed - CE.
-                  full_case: Passed - CE.
-                 full_case2: Passed - CE.
-               inside_synth: Passed - CE.
-              inside_synth3: Passed - CE.
                   memsynth1: Passed - CE.
                   memsynth2: Passed - CE.
                   memsynth3: Passed - CE.
@@ -17,6 +9,9 @@ Running compiler/VVP tests for Icarus Verilog version: 11.
                   memsynth7: Passed - CE.
                   memsynth9: Passed - CE.
                   mix_reset: Passed - CE.
+                      case1: Passed.
+                      case2: Passed.
+                casex_synth: Passed.
                       pr903: Passed.
                   pr1388974: Passed.
                    br_gh13a: Passed.
@@ -243,6 +238,7 @@ Running compiler/VVP tests for Icarus Verilog version: 11.
         array_lval_select3b: Passed - CE.
         array_lval_select4b: Passed - CE.
          array_lval_select6: Passed.
+            array_packed_2d: Passed.
                array_select: Passed.
              array_select_a: Passed.
            array_word_check: Passed.
@@ -1819,6 +1815,7 @@ test_mos_strength_reduction: Passed.
                 parpkg_test: Passed.
                parpkg_test2: Passed.
                parpkg_test3: Passed.
+              part_sel_port: Passed.
                      plus_5: Passed.
             plus_arg_string: Passed.
                   pr3366114: Passed.
@@ -1995,6 +1992,7 @@ test_mos_strength_reduction: Passed.
        undef_lval_select_SV: Passed.
           unp_array_typedef: Passed.
              ushortint_test: Passed.
+           vvp_recv_vec4_pv: Passed.
                   wait_fork: Passed.
                       work7: Passed.
                      work7b: Passed.
@@ -2027,21 +2025,28 @@ test_mos_strength_reduction: Passed.
                vhdl_boolean: Passed.
                 vhdl_concat: Passed.
            vhdl_concat_func: Passed.
+     vhdl_concurrent_assert: Passed.
          vhdl_const_package: Passed.
           vhdl_const_record: Passed.
            vhdl_const_array: Passed.
+          vhdl_delay_assign: Passed.
                  vhdl_expr1: Passed.
+            vhdl_elab_range: Passed.
           vhdl_generic_eval: Passed.
              vhdl_fa4_test1: Passed.
              vhdl_fa4_test2: Passed.
              vhdl_fa4_test3: Passed.
              vhdl_fa4_test4: Passed.
+             vhdl_file_open: Passed.
        vhdl_generic_default: Passed.
                   vhdl_init: Passed.
             vhdl_image_attr: Passed.
                  vhdl_inout: Passed.
         vhdl_labeled_assign: Passed.
+                  vhdl_lfcr: Passed.
                  vhdl_logic: Passed.
+                  vhdl_loop: Passed.
+        vhdl_multidim_array: ==> Failed - running iverilog.
       vhdl_nand104_stdlogic: Passed.
             vhdl_nand23_bit: Passed.
              vhdl_nandg_bit: Passed.
@@ -2055,12 +2060,14 @@ test_mos_strength_reduction: Passed.
       vhdl_notfunc_stdlogic: Passed.
               vhdl_notg_bit: Passed.
          vhdl_notg_stdlogic: Passed.
+                   vhdl_now: Passed.
         vhdl_or104_stdlogic: Passed.
               vhdl_or23_bit: Passed.
                vhdl_org_bit: Passed.
           vhdl_org_stdlogic: Passed.
           vhdl_prefix_array: Passed.
              vhdl_procedure: Passed.
+         vhdl_process_scope: Passed.
             vhdl_rand23_bit: Passed.
                  vhdl_range: Passed.
             vhdl_range_func: Passed.
@@ -2084,6 +2091,7 @@ test_mos_strength_reduction: Passed.
             vhdl_ssub23_bit: Passed.
        vhdl_ssub23_stdlogic: Passed.
           vhdl_struct_array: Passed.
+              vhdl_subtypes: Passed.
             vhdl_subprogram: Passed.
                 vhdl_string: Passed.
             vhdl_string_lim: Passed.
@@ -2124,6 +2132,7 @@ test_mos_strength_reduction: Passed.
                  basicexpr2: Passed.
                  basicexpr3: Passed.
                  basicexpr4: Passed.
+                 basiclatch: Passed.
                    basicreg: Passed.
                  basicstate: Passed.
                 basicstate2: Passed.
@@ -2147,7 +2156,7 @@ test_mos_strength_reduction: Passed.
                  casesynth4: Passed.
                  casesynth5: Passed.
                  casesynth6: Passed.
-                 casesynth7: Passed - CE.
+                 casesynth7: Passed.
                  casesynth8: Passed - CE.
                  casesynth9: Passed.
                     condit1: Passed.
@@ -2169,7 +2178,9 @@ test_mos_strength_reduction: Passed.
             for_loop_synth2: Passed.
             if_part_no_else: Passed.
            if_part_no_else2: Passed.
+               inside_synth: Passed.
               inside_synth2: Passed.
+              inside_synth3: Passed.
                       land5: Passed.
                   lcatsynth: Passed.
                   memsynth4: Passed.
@@ -2189,4 +2200,4 @@ test_mos_strength_reduction: Passed.
                 ufuncsynth1: Passed.
 ============================================================================
 Test results:
-  Total=2187, Passed=2181, Failed=6, Not Implemented=0, Expected Fail=0
+  Total=2198, Passed=2191, Failed=7, Not Implemented=0, Expected Fail=0