WTF bugs omg

LEDArrayController/baudrate-readme

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+We are running at close to 1MBAUD.
+
+THERE ARE ERRORS IN THIS RANGE
+
+but fuck it, the rate is acceptable

LEDArrayController/calc-rtlbaud.sci

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+// a short script to calaculate the baud rate generation parameters for the 
+// UART to Bus core 
+mode(-1)
+
+// define the GCD function since Scilab prefers to use a different function as gcd 
+function x = gcdn(a,b)
+x = zeros(length(b),length(a));
+for n=1:length(a),
+	for m=1:length(b),
+		x=a(n);
+		y=b(m);
+		while y~=0
+			r=modulo(x,y);
+			x=y;
+			y=r;
+		end 
+		x(m,n) = x;
+	end 
+end 
+endfunction 
+
+// request the required clock rate and baud rate parameters 
+dig_labels = ["Clock Frequency in MHz"; "UART Baud Rate in bps"];
+default_val = ["100"; "921600"];
+params = evstr(x_mdialog("Enter Core Parameters", dig_labels, default_val));
+
+// extract the parameters 
+global_clock_freq = params(1)*1e6;
+baud_rate = params(2);
+
+// calculate the baud rate generator parameters 
+D_BAUD_FREQ = 16*baud_rate / gcdn(global_clock_freq, 16*baud_rate);
+D_BAUD_LIMIT = (global_clock_freq / gcdn(global_clock_freq, 16*baud_rate)) - D_BAUD_FREQ;
+
+// print the values to the command window 
+printf("Calculated core baud rate generator parameters:\n");
+printf("    D_BAUD_FREQ  = 12''d%d\n", D_BAUD_FREQ);
+printf("    D_BAUD_LIMIT = 16''d%d\n", D_BAUD_LIMIT);
+
+// open a message with the calculated values 
+mes_str = ["Calculated core baud rate generator parameters:"; ...
+           "    D_BAUD_FREQ  = "+string(D_BAUD_FREQ); ...
+           "    D_BAUD_LIMIT = "+string(D_BAUD_LIMIT); ...
+           ""; ...
+           "The verilog definition can be copied from the following lines:"; ...
+           "`define D_BAUD_FREQ  12''d"+string(D_BAUD_FREQ); ...
+           "`define D_BAUD_LIMIT 16''d"+string(D_BAUD_LIMIT);
+           ];
+messagebox(mes_str);

LEDArrayController/rtl2-CURR-100MHZ/DE1_system.asm.rpt

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+Assembler report for DE1_system
+Mon May 28 17:10:38 2012
+Quartus II 32-bit Version 11.1 Build 173 11/01/2011 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Ian Finder/ledMonster/rtl2/DE1_system.sof
+  6. Assembler Device Options: C:/Users/Ian Finder/ledMonster/rtl2/DE1_system.pof
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2011 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Mon May 28 17:10:38 2012 ;
+; Revision Name         ; DE1_system                            ;
+; Top-level Entity Name ; DE1_system                            ;
+; Family                ; Cyclone II                            ;
+; Device                ; EP2C20F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; Off      ; Off           ;
+; Use configuration device                                                    ; On       ; On            ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Maintain Compatibility with All Cyclone II M4K Versions                     ; On       ; On            ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++----------------------------------------------------+
+; Assembler Generated Files                          ;
++----------------------------------------------------+
+; File Name                                          ;
++----------------------------------------------------+
+; C:/Users/Ian Finder/ledMonster/rtl2/DE1_system.sof ;
+; C:/Users/Ian Finder/ledMonster/rtl2/DE1_system.pof ;
++----------------------------------------------------+
+
+
++------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Ian Finder/ledMonster/rtl2/DE1_system.sof ;
++----------------+-------------------------------------------------------------+
+; Option         ; Setting                                                     ;
++----------------+-------------------------------------------------------------+
+; Device         ; EP2C20F484C6                                                ;
+; JTAG usercode  ; 0xFFFFFFFF                                                  ;
+; Checksum       ; 0x00201ED8                                                  ;
++----------------+-------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Ian Finder/ledMonster/rtl2/DE1_system.pof ;
++--------------------+---------------------------------------------------------+
+; Option             ; Setting                                                 ;
++--------------------+---------------------------------------------------------+
+; Device             ; EPCS16                                                  ;
+; JTAG usercode      ; 0x00000000                                              ;
+; Checksum           ; 0x1DD26FD9                                              ;
+; Compression Ratio  ; 3                                                       ;
++--------------------+---------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit Assembler
+    Info: Version 11.1 Build 173 11/01/2011 SJ Web Edition
+    Info: Processing started: Mon May 28 17:10:36 2012
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off LEDmonster -c DE1_system
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 295 megabytes
+    Info: Processing ended: Mon May 28 17:10:38 2012
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+

LEDArrayController/rtl2-CURR-100MHZ/DE1_system.done

@@ -0,0 +1 @@
+Mon May 28 17:10:41 2012

LEDArrayController/rtl2-CURR-100MHZ/DE1_system.eda.rpt

@@ -0,0 +1,96 @@
+EDA Netlist Writer report for DE1_system
+Mon May 28 17:10:40 2012
+Quartus II 32-bit Version 11.1 Build 173 11/01/2011 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2011 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Mon May 28 17:10:40 2012 ;
+; Revision Name             ; DE1_system                            ;
+; Top-level Entity Name     ; DE1_system                            ;
+; Family                    ; Cyclone II                            ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++---------------------------------------------------------------------------------+
+; Simulation Generated Files                                                      ;
++---------------------------------------------------------------------------------+
+; Generated Files                                                                 ;
++---------------------------------------------------------------------------------+
+; C:/Users/Ian Finder/ledMonster/rtl2/simulation/modelsim/DE1_system.vho          ;
+; C:/Users/Ian Finder/ledMonster/rtl2/simulation/modelsim/DE1_system_fast.vho     ;
+; C:/Users/Ian Finder/ledMonster/rtl2/simulation/modelsim/DE1_system_vhd.sdo      ;
+; C:/Users/Ian Finder/ledMonster/rtl2/simulation/modelsim/DE1_system_vhd_fast.sdo ;
++---------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit EDA Netlist Writer
+    Info: Version 11.1 Build 173 11/01/2011 SJ Web Edition
+    Info: Processing started: Mon May 28 17:10:39 2012
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off LEDmonster -c DE1_system
+Info (204026): Generated files "DE1_system.vho", "DE1_system_fast.vho", "DE1_system_vhd.sdo" and "DE1_system_vhd_fast.sdo" in directory "C:/Users/Ian Finder/ledMonster/rtl2/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 260 megabytes
+    Info: Processing ended: Mon May 28 17:10:40 2012
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+