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db
db
 
 
incremental_db
incremental_db
 
 
output_files
output_files
 
 
simulation/qsim
simulation/qsim
 
 
Adder.vhd
Adder.vhd
 
 
Adder.vhd.bak
Adder.vhd.bak
 
 
Lab2.zip
Lab2.zip
 
 
Logic_Processor.vhd
Logic_Processor.vhd
 
 
Logic_Processor.vhd.bak
Logic_Processor.vhd.bak
 
 
LogicalStep_Lab2.qpf
LogicalStep_Lab2.qpf
 
 
LogicalStep_Lab2.tcl
LogicalStep_Lab2.tcl
 
 
LogicalStep_Lab2_top.qsf
LogicalStep_Lab2_top.qsf
 
 
LogicalStep_Lab2_top.qws
LogicalStep_Lab2_top.qws
 
 
LogicalStep_Lab2_top.vhd
LogicalStep_Lab2_top.vhd
 
 
LogicalStep_Lab2_top.vhd.bak
LogicalStep_Lab2_top.vhd.bak
 
 
LogicalStep_Lab2_top_assignment_defaults.qdf
LogicalStep_Lab2_top_assignment_defaults.qdf
 
 
README.md
README.md
 
 
SevenSegment.vhd
SevenSegment.vhd
 
 
SevenSegment.vhd.bak
SevenSegment.vhd.bak
 
 
codeToFix.txt
codeToFix.txt
 
 
hex_mux.vhd
hex_mux.vhd
 
 
hex_mux.vhd.bak
hex_mux.vhd.bak
 
 
segment7_mux.vhd
segment7_mux.vhd
 
 
segment7_mux.vhd.bak
segment7_mux.vhd.bak
 
 

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Combinational_Logic_Circuit

In order to open the project execute the .qpf file in Quartus Prime (version 17.1 or higher). After that, open independent gates and see functionality of code in a FPGA board.

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fpga-board vhdl-code

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