or1k: allow get/set fcscr in userspace

FPU control status register setting and getting should be allowed in
use space as is allowed in all other architectures.  However, on
openrisc it is only alowed in privilaged mode.

Currently its not allowed but we need it for glibc.
Needs a spec change of patches to the kernel but this
gets things working for testing.

target/openrisc/translate.c

@@ -880,9 +880,6 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a)
 {
     check_r0_write(dc, a->d);
 
-    if (is_user(dc)) {
-        gen_illegal_exception(dc);
-    } else {
         TCGv spr = tcg_temp_new();
 
         if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
@@ -899,15 +896,11 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a)
         tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
         gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr);
         tcg_temp_free(spr);
-    }
     return true;
 }
 
 static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
 {
-    if (is_user(dc)) {
-        gen_illegal_exception(dc);
-    } else {
         TCGv spr;
 
         if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
@@ -930,7 +923,6 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
         tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
         gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b));
         tcg_temp_free(spr);
-    }
     return true;
 }