Fix SYSCFG CFGR3 register fields

I have compared the result against all 3 reference manuals and it looks correct.
stm32-rs · Nov 1, 2019 · 8b5eb0a · 8b5eb0a
1 parent ede1455
commit 8b5eb0a
Show file tree

Hide file tree

Showing 4 changed files with 26 additions and 3 deletions.
diff --git a/devices/common_patches/l0_syscfg_cfgr.yaml b/devices/common_patches/l0_syscfg_cfgr.yaml
@@ -26,6 +26,7 @@ SYSCFG:
       - FWDISEN
   CFGR3:
     _delete:
+      - REF_LOCK
       - VREFINT_COMP_RDYF
       - VREFINT_ADC_RDYF
       - SENSOR_ADC_RDYF
@@ -35,6 +36,12 @@ SYSCFG:
       - ENBUF_BGAP_ADC
       - EN_BGAP
     _add:
+      # REF_LOCK is wrongly marked as writeable
+      REF_LOCK:
+        description: SYSCFG_CFGR3 lock bit
+        bitOffset: 31
+        bitWidth: 1
+        access: read-only
       ENBUF_VREFINT_COMP2:
         description: VREFINT reference for COMP2 scaler enable bit
         bitOffset: 12
@@ -46,4 +53,4 @@ SYSCFG:
       EN_VREFINT:
         description: VREFINT enable and scaler control for COMP2 enable bit
         bitOffset: 0
-        bitWidth: 1
+        bitWidth: 1
diff --git a/devices/stm32l0x1.yaml b/devices/stm32l0x1.yaml
@@ -67,7 +67,7 @@ RCC:
       I2C3:
         name: I2C3RST
   CCIPR:
-    _merge: 
+    _merge:
       - "LPTIM1SEL*"
       - "I2C3SEL*"
       - "I2C1SEL*"

diff --git a/devices/stm32l0x2.yaml b/devices/stm32l0x2.yaml
@@ -63,7 +63,7 @@ RCC:
       CSSLSEON:
         name: CSSHSEON
   CCIPR:
-    _merge: 
+    _merge:
       - "LPTIM1SEL*"
       - "I2C1SEL*"
       - "LPUART1SEL*"
@@ -78,6 +78,14 @@ RCC:
       TM12RST:
         name: TIM22RST
 
+SYSCFG:
+  CFGR3:
+    _add:
+      ENREF_HSI48:
+        description: VREFINT reference for HSI48 oscillator enable bit
+        bitOffset: 13
+        bitWidth: 1
+
 PWR:
   CR:
     _add:

diff --git a/devices/stm32l0x3.yaml b/devices/stm32l0x3.yaml
@@ -89,6 +89,14 @@ RCC:
       TM12RST:
         name: TIM22RST
 
+SYSCFG:
+  CFGR3:
+    _add:
+      ENREF_HSI48:
+        description: VREFINT reference for HSI48 oscillator enable bit
+        bitOffset: 13
+        bitWidth: 1
+
 PWR:
   CR:
     _add: