L4 and WB fixes

devices/common_patches/stm32l4x2_l412.yaml

@@ -0,0 +1,132 @@
+# Common patches and includes for L4x2 and L412.
+
+# SVD incorrectly labels APB1ENR1 bit 18 as USART1EN instead of USART3EN.
+# SVD incorrectly labels APB1ENR1 bit 26 as USBF instead of USBFSEN.
+# SVD incorrectly labels APB1ENR1 bit 14 as SPI1EN instead of SPI2EN.
+# SVD incorrectly omits APB1ENR1 bit 1 (TIM3RST), which is present for
+# STM32L45xx and STM32L46xx devices.
+RCC:
+  APB1ENR1:
+    _modify:
+      USART1EN:
+        name: USART3EN
+        description: USART3 clock enable
+      USBF:
+        name: USBFSEN
+        description: USB FS clock enable
+      SPI1EN:
+        name: SPI2EN
+        description: SPI2 clock enable
+  APB1RSTR1:
+    _modify:
+      USART1RST:
+        name: USART3RST
+        description: USART3 reset
+    _add:
+      TIM3RST:
+        description: TIM3 timer reset
+        bitOffset: 1
+        bitWidth: 1
+        access: read-write
+
+_modify:
+  USB_SRAM:
+     name: USB
+     # without quotes, get less readable value 1073768448
+     baseAddress: "0x40006800"
+
+  # The SVD calls ADC1 ADC.
+  ADC:
+    name: ADC1
+
+ADC1:
+  _modify:
+    _interrupts:
+      ADC1:
+        name: ADC1_2
+
+_add:
+  ADC2:
+    derivedFrom: ADC1
+    baseAddress: "0x50040100"
+
+USB:
+  _add:
+    _interrupts:
+      USB_FS:
+        description: USB event interrupt through EXTI
+        value: 67
+
+_delete:
+  - USB_FS
+
+# Merge the thousands of individal bit fields into a single field for each
+# CAN filter register. This is not only much easier to use but also saves
+# a huge amount of filespace and compilation time etc -- as much as 30% of all
+# fields in many devices are just these CAN filter bank fields.
+"CAN*":
+  "F?R?":
+    _merge:
+      - "FB*"
+  "F??R?":
+    _merge:
+      - "FB*"
+
+# TIM3 is 16-bit, whilst TIM2 is 32-bit
+_copy:
+  TIM3:
+    from: TIM2
+
+# NB: Paths here are relative to the common_patches directory.
+_include:
+ - 4_nvic_prio_bits.yaml
+ - merge_USART_CR1_DEATx_fields.yaml
+ - merge_USART_CR2_ADDx_fields.yaml
+ - merge_USART_CR2_ABRMODx_fields.yaml
+ - merge_USART_CR1_DEDTx_fields.yaml
+ - rename_USART_CR2_DATAINV_field.yaml
+ - merge_LPUART_CR1_DEATx_fields.yaml
+ - merge_LPUART_CR1_DEDTx_fields.yaml
+ - rename_LPUART_CR2_DATAINV_field.yaml
+ - merge_LPUART_CR2_ADDx_fields.yaml
+ - merge_USART_BRR_fields.yaml
+ - can/can.yaml
+ - can/can_filter_bank.yaml
+ - ../../peripherals/can/can.yaml
+ - sai/sai_v1.yaml
+ - dfsdm/dfsdm_v2.yaml
+ - ../../peripherals/gpio/gpio_v2.yaml
+ - crc/crc_rename_init.yaml
+ - ../../peripherals/crc/crc_advanced.yaml
+ - ../../peripherals/crc/crc_idr_8bit.yaml
+ - ../../peripherals/crc/crc_with_polysize.yaml
+ - ../../peripherals/wwdg/wwdg.yaml
+ - ../../peripherals/rcc/rcc_l4.yaml
+ - tim/common.yaml
+ - ../../peripherals/tim/tim_basic.yaml
+ - ../../peripherals/tim/tim16.yaml
+ - ../../peripherals/tim/tim6.yaml
+ - ../../peripherals/tim/tim2345_mixed.yaml
+ - tim/tim2345_mixed_l.yaml
+ - ../../peripherals/tim/tim_advanced.yaml
+ - tim/tim_ccr.yaml
+ - tim/v2/l4.yaml
+ - ../../peripherals/tim/v2/ccm.yaml
+ - ../../peripherals/dma/dma_v1_with_remapping.yaml
+ - ../../peripherals/iwdg/iwdg_with_WINR.yaml
+ - ../../peripherals/exti/exti.yaml
+ - ../../peripherals/i2c/i2c_v2.yaml
+ - ../../peripherals/usart/lpuart_v2A.yaml
+ - ../../peripherals/usart/usart_v2B2.yaml
+ - rtc/rtc_cr.yaml
+ - tsc/tsc.yaml
+ - fpu_interrupt.yaml
+ - ../../peripherals/usb/usb_array.yaml
+ - ../../peripherals/usb/usb_with_LPM.yaml
+ - flash/flash_boot0s.yaml
+ - ../../peripherals/sai/sai.yaml
+ - l4_adc_common.yaml
+ - l4_adc_smpr.yaml
+ - l4_adc_sqr1.yaml
+ - l4_spi.yaml
+ - ../../peripherals/spi/spi_l4.yaml

devices/stm32l412.yaml

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+# This SVD is a copy+paste of l4x2's.
+_svd: ../svd/stm32l412.svd
+
+# This module is the same as l4x2, but with the RTC peripheral from L5 and G4.
+# Applies to L412 and L422 MCUs. Note that the RM (RM0394) includes two separate
+# RTC chapters: One that applies to L41x and L42x (Chapter 34), and one that 
+# applies to the rest. (Chapter 36). This module includes the Chapter 34 RTC setup.
+
+# TR, DR, PRER, WPR, TSSSR, SHIFTR, TSTR, TSDR, ALRMASSR,registers unchanged.
+# old CR at new address, and some fields added
+# WUTR has an additional WUTOCLR field.
+# CR has additional fields.
+# CALR, SSR, SHIFTR, ALRMAR and ALRMBR, ALRMASSR, ALRMBSSR at a diff address.
+# CALR has an added field.
+# ISR, TAMPCR, OR, BKP0R, and BKP31R removed.
+# SCR, MISR, SR, ICSR added
+
+RTC:
+  _delete:
+    - ISR
+    - TAMPCR
+    - OR
+    - BKP*R
+
+  _modify:
+    SSR:
+      addressOffset: 0x08
+
+    CR:
+      addressOffset: 0x18
+
+    CALR:
+      addressOffset: 0x28
+
+    SHIFTR:
+      addressOffset: 0x2c
+
+    ALRMAR:
+      addressOffset: 0x40
+
+    ALRMBR:
+      addressOffset: 0x48
+
+    ALRMBSSR:
+      addressOffset: 0x4c
+
+  WUTR:
+    _add:
+        WUTOCLR:
+          description: Wakeup auto-reload output clear value
+          bitOffset: 16
+          bitWidth: 16
+          access: read-write
+
+  CALR:     
+    _add:
+      LPCAL:
+        description: Calibration low-power mode
+        bitOffset: 12
+        bitWidth: 1
+        access: read-write
+
+  CR:
+    _add:
+      TAMPTS:
+        description: Activate timestamp on tamper detection event
+        bitOffset: 25
+        bitWidth: 1
+        access: read-write
+      TAMPOE:
+        description: Tamper detection output enable on TAMPALRM
+        bitOffset: 26
+        bitWidth: 1
+        access: read-write
+      TAMPALRM_PU:
+        description: TAMPALRM pull-up enable
+        bitOffset: 29
+        bitWidth: 1
+        access: read-write
+      TAMPALRM_TYPE:
+        description: TAMPALRM output type
+        bitOffset: 30
+        bitWidth: 1
+        access: read-write
+      OUT2EN:
+        description: RTC_OUT2 output enable
+        bitOffset: 31
+        bitWidth: 1
+        access: read-write
+
+  _add:
+    ICSR:
+      description: RTC initialization control and status register
+      addressOffset: 0x0c
+      size: 0x20
+      access: read-write
+      resetValue: 0x00000007
+      fields:
+        WUTWF:
+          description: Wakeup timer write flag
+          bitOffset: 2
+          bitWidth: 1
+          access: read-only
+        SHPF:
+          description: Shift operation pending
+          bitOffset: 3
+          bitWidth: 1
+          access: read-only
+        INITS:
+          description: Initialization status flag
+          bitOffset: 4
+          bitWidth: 1
+          access: read-only
+        RSF:
+          description: Registers synchronization flag
+          bitOffset: 5
+          bitWidth: 1
+        INITF:
+          description: Initialization flag
+          bitOffset: 6
+          bitWidth: 1
+          access: read-only
+        INIT:
+          description: Initialization mode
+          bitOffset: 7
+          bitWidth: 1
+        RECALPF:
+          description: Recalibration pending Flag
+          bitOffset: 16
+          bitWidth: 1
+          access: read-only
+
+    SR:
+      description: RTC status register
+      addressOffset: 0x50
+      size: 0x20
+      access: read-only
+      resetValue: 0x00000000
+      fields:
+        ALRAF:
+          description: Alarm A flag
+          bitOffset: 0
+          bitWidth: 1
+        ALRBF:
+          description: Alarm B flag
+          bitOffset: 1
+          bitWidth: 1
+        WUTF:
+          description: Wakeup timer flag
+          bitOffset: 2
+          bitWidth: 1
+        TSF:
+          description: Timestamp flag
+          bitOffset: 3
+          bitWidth: 1
+        TSOVF:
+          description: Timestamp overflow flag
+          bitOffset: 4
+          bitWidth: 1
+        ITSF:
+          description: Internal timestamp flag
+          bitOffset: 5
+          bitWidth: 1
+
+    MISR:
+      description: RTC masked interrupt status register
+      addressOffset: 0x54
+      size: 0x20
+      access: read-only
+      resetValue: 0x00000000
+      fields:
+        ALRAMF:
+          description: Alarm A masked flag
+          bitOffset: 0
+          bitWidth: 1
+        ALRBMF:
+          description: Alarm B masked flag
+          bitOffset: 1
+          bitWidth: 1
+        WUTMF:
+          description: Wakeup timer masked flag
+          bitOffset: 2
+          bitWidth: 1
+        TSMF:
+          description: Timestamp masked flag
+          bitOffset: 3
+          bitWidth: 1
+        TSOVMF:
+          description: Timestamp overflow masked flag
+          bitOffset: 4
+          bitWidth: 1
+        ITSMF:
+          description: Internal timestamp masked flag
+          bitOffset: 5
+          bitWidth: 1
+
+    SCR:
+      description: RTC status clear register
+      addressOffset: 0x5c
+      size: 0x20
+      access: write-only
+      resetValue: 0x00000000
+      fields:
+        CALRAF:
+          description: Clear alarm A flag
+          bitOffset: 0
+          bitWidth: 1
+        CALRBF:
+          description: Clear alarm B flag
+          bitOffset: 1
+          bitWidth: 1
+        CWUTF:
+          description: Clear wakeup timer flag
+          bitOffset: 2
+          bitWidth: 1
+        CTSF:
+          description: Clear timestamp flag
+          bitOffset: 3
+          bitWidth: 1
+        CTSOVF:
+          description: Clear timestamp overflow flag
+          bitOffset: 4
+          bitWidth: 1
+        CITSF:
+          description: Clear internal timestamp flag
+          bitOffset: 5
+          bitWidth: 1
+
+# Most of the other patches for this device are common with the L4x2 device.
+_include:
+  - ./common_patches/stm32l4x2_l412.yaml