Merge pull request #212 from Sh3Rm4n/more-tests

Add more tests

.cargo/config.toml

@@ -8,12 +8,14 @@
 # and only avaliable under the -Z extra-link-arg flag.
 # See https://github.com/rust-lang/cargo/pull/8441
 [target.thumbv7em-none-eabihf]
-runner = "arm-none-eabi-gdb"
+# runner = "arm-none-eabi-gdb"
 # Chip can be set via `--chip STM32F303VCTx` or `export PROBE_RUN_CHIP=STM32F303VCTx`
-# runner = "probe-run"
+runner = "probe-run --chip STM32F303VCTx --connect-under-reset"
 rustflags = [
+  "-C", "link-arg=--nmagic",
   "-C", "link-arg=-Tlink.x",
-  # "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=-Tdefmt.x",
+  # "-C", "linker=flip-link",
 ]
 
 [build]

.github/workflows/ci.yml

@@ -92,16 +92,9 @@ jobs:
           command: check
           args: --features=stm32f303xc,stm32-usbd,rt,can,ld --lib --examples
 
-  check-tests:
-    name: Check Tests
+  build-testsuite:
+    name: Build Testsuite
     runs-on: ubuntu-latest
-    strategy:
-      matrix:
-        test:
-          - rcc
-        mcu:
-          - stm32f303xc
-          - stm32f303xd
     steps:
       - uses: actions/checkout@v2
       - uses: actions-rs/toolchain@v1
@@ -112,8 +105,8 @@ jobs:
           profile: minimal
       - uses: actions-rs/cargo@v1
         with:
-          command: check
-          args: --features=ld,defmt,${{ matrix.mcu }} --test ${{ matrix.test }}
+          command: test
+          args: -p testsuite --no-run
 
   check-doc:
     name: Check Documentation Build
@@ -177,7 +170,7 @@ jobs:
           override: true
           profile: minimal
           components: rustfmt
-      - run: cd codegen && cargo check
+      - run: cargo check --target "x86_64-unknown-linux-gnu" -p codegen
 
   markdown-lint:
     name: Markdown Lint

CHANGELOG.md

@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Support for GPIO interrupts ([#189])
 - `ld` feature, which enables the memory.x generation ([#216])
 - Implement `DelayMs` for `Milliseconds` and `DelayUs` for `Microseconds` ([#234])
+- ADC can now be `free()`'d ([#212])
 
 ### Changed
 
@@ -44,11 +45,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 // The supplied frequencies must be in `MHz`.
 let clocks = rcc
     .cfgr
-    .use_hse(8u32.MHz())
-    .hclk(48u32.MHz())
-    .sysclk(48u32.MHz())
-    .pclk1(12u32.MHz())
-    .pclk2(12u32.MHz())
+    .use_hse(8.MHz())
+    .hclk(48.MHz())
+    .sysclk(48.MHz())
+    .pclk1(12.MHz())
+    .pclk2(12.MHz())
 ```
 
 - You always required to select a sub-target for target chips ([#216])
@@ -329,6 +330,7 @@ let clocks = rcc
 [#220]: https://github.com/stm32-rs/stm32f3xx-hal/pull/220
 [#217]: https://github.com/stm32-rs/stm32f3xx-hal/pull/217
 [#216]: https://github.com/stm32-rs/stm32f3xx-hal/pull/216
+[#212]: https://github.com/stm32-rs/stm32f3xx-hal/pull/212
 [#210]: https://github.com/stm32-rs/stm32f3xx-hal/pull/210
 [#208]: https://github.com/stm32-rs/stm32f3xx-hal/pull/208
 [#203]: https://github.com/stm32-rs/stm32f3xx-hal/issues/203

Cargo.toml

@@ -20,6 +20,13 @@ exclude = [
 ]
 resolver = "2"
 
+[workspace]
+members = [
+    ".",
+    "testsuite",
+    "codegen"
+]
+
 [package.metadata.docs.rs]
 features = ["stm32f303xc", "rt", "stm32-usbd", "can"]
 targets = ["thumbv7em-none-eabihf"]
@@ -134,15 +141,27 @@ defmt-info = ["defmt"]
 defmt-warn = ["defmt"]
 defmt-error = ["defmt"]
 
+# cargo build/run
 [profile.dev]
-debug = true
+debug = 2
 lto = true
 
+# cargo test
+[profile.test]
+debug = 2
+opt-level = 3 # <-
+
+# cargo build/run --release
 [profile.release]
-debug = true
+debug = 2
 lto = true
 opt-level = "s"
 
+# cargo test --release
+[profile.bench]
+debug = 2
+opt-level = "s"
+
 [[example]]
 name = "pwm"
 required-features = ["ld", "stm32f303xc"]
@@ -186,8 +205,3 @@ required-features = ["ld", "stm32f303xc"]
 [[example]]
 name = "gpio_interrupts"
 required-features = ["ld", "rt", "stm32f303xc"]
-
-[[test]]
-name = "rcc"
-required-features = ["ld", "defmt"]
-harness = false

README.md

@@ -170,18 +170,5 @@ compile with older versions but that may change in any new patch release.
 
 ### Running Tests
 
-Tests are run via the integration test pattern and are executed on a target
-chip, rather than on a host system. First, install
-[probe-run](https://crates.io/crates/probe-run) via `cargo install probe-run`.
-Next, you'll need to modify `.cargo/config` to link defmt and use `probe-run`
-configured for your chip. See details within the comments in that file.
-
-Now, you can execute a test by setting your device, defmt, and any test specific
-features:
-
-```bash
-cargo test --test rcc --features=stm32f303xc,defmt,rt
-```
-
-The result _always_ shows a backtrace, even in the case of success.
-Exit code of 0 means that the run was successful.
+See [`testsuite/README.md`](testsuite/README.md) for how to set up and run
+tests on the target.

build.rs

@@ -169,11 +169,26 @@ This may be due to incorrect feature configuration in Cargo.toml or stm32f3xx-ha
     let out_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap());
     let mut file = File::create(out_dir.join("memory.x")).unwrap();
     writeln!(file, "MEMORY {{").unwrap();
-    writeln!(file, "    FLASH (rx) : o = 0x8000000, l = {}K", flash).unwrap();
+    writeln!(
+        file,
+        "    FLASH (rx) : ORIGIN = 0x8000000, LENGTH = {}K",
+        flash
+    )
+    .unwrap();
     if ccmram > 0 {
-        writeln!(file, "    CCMRAM (rwx) : o = 0x10000000, l = {}K", ccmram).unwrap();
+        writeln!(
+            file,
+            "    CCMRAM (rwx) : ORIGIN = 0x10000000, LENGTH = {}K",
+            ccmram
+        )
+        .unwrap();
     }
-    writeln!(file, "    RAM (rwx) : o = 0x20000000, l = {}K", ram).unwrap();
+    writeln!(
+        file,
+        "    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = {}K",
+        ram
+    )
+    .unwrap();
     writeln!(file, "}}").unwrap();
     println!("cargo:rustc-link-search={}", out_dir.display());
 }

examples/adc.rs

@@ -32,8 +32,8 @@ fn main() -> ! {
 
     // Set up pin PA0 as analog pin.
     // This pin is connected to the user button on the stm32f3discovery board.
-    let mut gpio_a = dp.GPIOA.split(&mut rcc.ahb);
-    let mut adc1_in1_pin = gpio_a.pa0.into_analog(&mut gpio_a.moder, &mut gpio_a.pupdr);
+    let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
+    let mut adc1_in1_pin = gpioa.pa0.into_analog(&mut gpioa.moder, &mut gpioa.pupdr);
 
     // Be aware that the values in the table below depend on the input of VREF.
     // To have a stable VREF input, put a condensator and a volt limiting diode in front of it.

examples/can.rs

@@ -31,10 +31,10 @@ fn main() -> ! {
 
     let _clocks = rcc
         .cfgr
-        .use_hse(32u32.MHz())
-        .sysclk(32u32.MHz())
-        .pclk1(16u32.MHz())
-        .pclk2(16u32.MHz())
+        .use_hse(32.MHz())
+        .sysclk(32.MHz())
+        .pclk1(16.MHz())
+        .pclk2(16.MHz())
         .freeze(&mut flash.acr);
 
     // Configure CAN RX and TX pins (AF9)
@@ -58,13 +58,13 @@ fn main() -> ! {
         .into_push_pull_output(&mut gpiob.moder, &mut gpiob.otyper);
     led0.set_high().unwrap();
 
-    let filter = CanFilter::from_mask(0b100, ID as u32);
+    let filter = CanFilter::from_mask(0b100, ID.into());
     rx0.set_filter(filter);
 
     // Watchdog makes sure this gets restarted periodically if nothing happens
     let mut iwdg = IndependentWatchDog::new(dp.IWDG);
     iwdg.stop_on_debug(&dp.DBGMCU, true);
-    iwdg.start(100u32.milliseconds());
+    iwdg.start(100.milliseconds());
 
     // Send an initial message!
     asm::delay(100_000);

examples/i2c_scanner.rs

@@ -41,7 +41,7 @@ fn main() -> ! {
     let mut i2c = hal::i2c::I2c::new(
         dp.I2C1,
         (scl, sda),
-        100u32.kHz().try_into().unwrap(),
+        100.kHz().try_into().unwrap(),
         clocks,
         &mut rcc.apb1,
     );

examples/pwm.rs

@@ -28,7 +28,7 @@ fn main() -> ! {
     // Configure our clocks
     let mut flash = dp.FLASH.constrain();
     let mut rcc = dp.RCC.constrain();
-    let clocks = rcc.cfgr.sysclk(16u32.MHz()).freeze(&mut flash.acr);
+    let clocks = rcc.cfgr.sysclk(16.MHz()).freeze(&mut flash.acr);
 
     // Prep the pins we need in their correct alternate function
     let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
@@ -72,9 +72,9 @@ fn main() -> ! {
     // A four channel general purpose timer that's broadly available
     let tim3_channels = tim3(
         dp.TIM3,
-        1280,       // resolution of duty cycle
-        50u32.Hz(), // frequency of period
-        &clocks,    // To get the timer's clock speed
+        1280,    // resolution of duty cycle
+        50.Hz(), // frequency of period
+        &clocks, // To get the timer's clock speed
     );
 
     // Channels without pins cannot be enabled, so we can't forget to
@@ -121,9 +121,9 @@ fn main() -> ! {
     // A 32-bit timer, so we can set a larger resolution
     let tim2_channels = tim2(
         dp.TIM2,
-        160000,     // resolution of duty cycle
-        50u32.Hz(), // frequency of period
-        &clocks,    // To get the timer's clock speed
+        160000,  // resolution of duty cycle
+        50.Hz(), // frequency of period
+        &clocks, // To get the timer's clock speed
     );
 
     let mut tim2_ch3 = tim2_channels.2.output_to_pb10(pb10);
@@ -136,9 +136,9 @@ fn main() -> ! {
     // just use it directly
     let mut tim16_ch1 = tim16(
         dp.TIM16,
-        1280,       // resolution of duty cycle
-        50u32.Hz(), // frequency of period
-        &clocks,    // To get the timer's clock speed
+        1280,    // resolution of duty cycle
+        50.Hz(), // frequency of period
+        &clocks, // To get the timer's clock speed
     )
     .output_to_pb8(pb8);
     tim16_ch1.set_duty(tim16_ch1.get_max_duty() / 20); // 5% duty cyle

examples/spi.rs

@@ -26,9 +26,9 @@ fn main() -> ! {
 
     let clocks = rcc
         .cfgr
-        .use_hse(8u32.MHz())
-        .sysclk(48u32.MHz())
-        .pclk1(24u32.MHz())
+        .use_hse(8.MHz())
+        .sysclk(48.MHz())
+        .pclk1(24.MHz())
         .freeze(&mut flash.acr);
 
     // Configure pins for SPI

examples/usb_serial.rs

@@ -26,10 +26,10 @@ fn main() -> ! {
 
     let clocks = rcc
         .cfgr
-        .use_hse(8u32.MHz())
-        .sysclk(48u32.MHz())
-        .pclk1(24u32.MHz())
-        .pclk2(24u32.MHz())
+        .use_hse(8.MHz())
+        .sysclk(48.MHz())
+        .pclk1(24.MHz())
+        .pclk2(24.MHz())
         .freeze(&mut flash.acr);
 
     assert!(clocks.usbclk_valid());