Skip to content

Commit

Permalink
f4 dma
Browse files Browse the repository at this point in the history
  • Loading branch information
@burrbull
burrbull committed May 4, 2023
1 parent 7bfe0f7 commit 388ba83
Show file tree
Hide file tree
Showing 3 changed files with 131 additions and 104 deletions.
7 changes: 4 additions & 3 deletions Cargo.toml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -616,6 +616,8 @@ dma = []
uart_v1 = []
uart_v2 = []
usb_hs_phy = []
dfsdm = []
sai = []

adc2 = []
adc3 = []
Expand All @@ -636,7 +638,6 @@ crs = []
dac = []
dcmi = []
debug = []
dfsdm = []
dfsdm1 = ["dfsdm"]
dfsdm2 = ["dfsdm"]
dsihost = []
Expand Down Expand Up @@ -694,8 +695,8 @@ pwr = []
rf = []
rng = []
rtc = []
sai1 = []
sai2 = []
sai1 = ["sai"]
sai2 = ["sai"]
sai3 = []
sai4 = []
sdio = []
Expand Down
19 changes: 19 additions & 0 deletions src/dma/traits.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -361,3 +361,22 @@ pub struct FLT<T, const F: u8> {

#[cfg(feature = "dfsdm")]
impl<T, const F: u8> crate::Sealed for FLT<T, F> {}

#[cfg(feature = "sai")]
pub struct SAICH<T, const C: u8> {
_per: PhantomData<T>,
}

#[cfg(feature = "sai")]
impl<T, const C: u8> crate::Sealed for SAICH<T, C> {}

dma_map!(
(Stream0<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream1<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream2<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream3<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream4<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream5<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream6<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream7<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
);
209 changes: 108 additions & 101 deletions src/dma/traits/f4.rs
View file
Original file line number Diff line number Diff line change
@@ -1,57 +1,21 @@
use super::*;

#[cfg(any(
feature = "gpio-f401",
feature = "gpio-f417",
feature = "gpio-f411",
feature = "gpio-f412",
feature = "gpio-f413",
feature = "gpio-f427",
feature = "gpio-f446",
feature = "gpio-f469",
))]
#[cfg(feature = "tim1")]
dma_map!(
(Stream0<DMA1>:2, timer::CCR1<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH1
(Stream2<DMA1>:5, timer::CCR4<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4
(Stream2<DMA1>:5, timer::DMAR<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_UP
(Stream3<DMA1>:2, timer::CCR2<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH2
(Stream4<DMA1>:5, timer::CCR1<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1
(Stream4<DMA1>:5, timer::DMAR<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_TRIG
(Stream5<DMA1>:3, timer::CCR1<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
(Stream5<DMA1>:5, timer::CCR2<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH2
(Stream6<DMA1>:2, timer::DMAR<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_UP
(Stream6<DMA1>:3, timer::CCR2<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
(Stream6<DMA1>:3, timer::CCR4<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
(Stream7<DMA1>:2, timer::CCR3<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH3
(Stream7<DMA1>:5, timer::CCR3<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3
(Stream0<DMA1>:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX
(Stream2<DMA1>:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX
(Stream4<DMA1>:3, pac::I2C3, [MemoryToPeripheral]), //I2C3_TX
(Stream5<DMA1>:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX
(Stream7<DMA1>:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX
);

#[cfg(any(
feature = "gpio-f401",
feature = "gpio-f417",
feature = "gpio-f411",
feature = "gpio-f412",
feature = "gpio-f413",
feature = "gpio-f427",
feature = "gpio-f446",
feature = "gpio-f469",
))]
address!((pac::SPI3, dr, u8), (pac::I2C3, dr, u8),);

#[cfg(not(any(feature = "gpio-f410")))]
dma_map!(
(Stream3<DMA2>:4, pac::SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO
(Stream6<DMA2>:4, pac::SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO
(Stream0<DMA2>:6, timer::DMAR<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG
(Stream1<DMA2>:6, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
(Stream2<DMA2>:6, timer::CCR2<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2
(Stream3<DMA2>:6, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
(Stream4<DMA2>:6, timer::CCR4<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH4
(Stream4<DMA2>:6, timer::DMAR<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG/COM
(Stream5<DMA2>:6, timer::DMAR<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_UP
(Stream6<DMA2>:0, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
(Stream6<DMA2>:0, timer::CCR2<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2
(Stream6<DMA2>:0, timer::CCR3<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3
(Stream6<DMA2>:6, timer::CCR3<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3
);

#[cfg(not(any(feature = "gpio-f410")))]
address!((pac::SDIO, fifo, u32),);

#[cfg(feature = "tim5")]
dma_map!(
(Stream0<DMA1>:6, timer::CCR3<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH3
(Stream0<DMA1>:6, timer::DMAR<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP
Expand All @@ -62,27 +26,19 @@ dma_map!(
(Stream3<DMA1>:6, timer::DMAR<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_TRIG
(Stream4<DMA1>:6, timer::CCR2<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH2
(Stream6<DMA1>:6, timer::DMAR<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP
(Stream0<DMA2>:6, timer::DMAR<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG
(Stream1<DMA2>:6, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
(Stream2<DMA2>:6, timer::CCR2<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2
(Stream3<DMA2>:6, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
(Stream4<DMA2>:6, timer::CCR4<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH4
(Stream4<DMA2>:6, timer::DMAR<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG/COM
(Stream5<DMA2>:6, timer::DMAR<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_UP
(Stream6<DMA2>:0, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
(Stream6<DMA2>:0, timer::CCR2<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2
(Stream6<DMA2>:0, timer::CCR3<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3
(Stream6<DMA2>:6, timer::CCR3<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3
(Stream0<DMA1>:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX
(Stream2<DMA1>:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX
);

dma_map!(
(Stream0<DMA1>:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX
(Stream2<DMA1>:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX
(Stream3<DMA1>:0, pac::SPI2, [PeripheralToMemory]), //SPI2_RX
(Stream3<DMA1>:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX
(Stream4<DMA1>:0, pac::SPI2, [MemoryToPeripheral]), // SPI2_TX
(Stream5<DMA1>:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX
(Stream5<DMA1>:4, pac::USART2, [PeripheralToMemory]), //USART2_RX
(Stream6<DMA1>:4, pac::USART2, [MemoryToPeripheral]), //USART2_TX
(Stream7<DMA1>:7, pac::I2C2, [MemoryToPeripheral]), //I2C2_TX
(Stream0<DMA2>:0, pac::ADC1, [PeripheralToMemory]),
(Stream0<DMA2>:0, pac::ADC1, [PeripheralToMemory]), //ADC1
(Stream0<DMA2>:3, pac::SPI1, [PeripheralToMemory]), //SPI1_RX
(Stream1<DMA2>:5, pac::USART6, [PeripheralToMemory]), //USART6_RX
(Stream2<DMA2>:3, pac::SPI1, [PeripheralToMemory]), //SPI1_RX
Expand All @@ -93,14 +49,6 @@ dma_map!(
(Stream6<DMA2>:5, pac::USART6, [MemoryToPeripheral]), //USART6_TX
(Stream7<DMA2>:4, pac::USART1, [MemoryToPeripheral]), //USART1_TX
(Stream7<DMA2>:5, pac::USART6, [MemoryToPeripheral]), //USART6_TX
(Stream0<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream1<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream2<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream3<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream4<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream5<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream6<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
(Stream7<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
);

address!(
Expand All @@ -114,6 +62,51 @@ address!(
(pac::USART6, dr, u8),
);

#[cfg(any(
feature = "gpio-f401",
feature = "gpio-f417",
feature = "gpio-f411",
feature = "gpio-f412",
feature = "gpio-f413",
feature = "gpio-f427",
feature = "gpio-f446",
feature = "gpio-f469",
))]
dma_map!(
(Stream0<DMA1>:2, timer::CCR1<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH1
(Stream2<DMA1>:5, timer::CCR4<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4
(Stream2<DMA1>:5, timer::DMAR<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_UP
(Stream3<DMA1>:2, timer::CCR2<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH2
(Stream4<DMA1>:5, timer::CCR1<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1
(Stream4<DMA1>:5, timer::DMAR<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_TRIG
(Stream5<DMA1>:3, timer::CCR1<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
(Stream5<DMA1>:5, timer::CCR2<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH2
(Stream6<DMA1>:2, timer::DMAR<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_UP
(Stream6<DMA1>:3, timer::CCR2<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
(Stream6<DMA1>:3, timer::CCR4<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
(Stream7<DMA1>:2, timer::CCR3<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH3
(Stream7<DMA1>:5, timer::CCR3<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3
(Stream0<DMA1>:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX
(Stream2<DMA1>:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX
(Stream4<DMA1>:3, pac::I2C3, [MemoryToPeripheral]), //I2C3_TX
(Stream5<DMA1>:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX
(Stream7<DMA1>:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX
);

#[cfg(feature = "i2c3")]
address!((pac::I2C3, dr, u8),);
#[cfg(feature = "spi3")]
address!((pac::SPI3, dr, u8),);

#[cfg(feature = "sdio")]
dma_map!(
(Stream3<DMA2>:4, pac::SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO
(Stream6<DMA2>:4, pac::SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO
);

#[cfg(feature = "sdio")]
address!((pac::SDIO, fifo, u32),);

#[cfg(any(
feature = "gpio-f401",
feature = "gpio-f411",
Expand Down Expand Up @@ -336,7 +329,6 @@ dma_map!(
(Stream7<DMA1>:4, pac::FMPI2C1, [MemoryToPeripheral]), //FMPI2C1_TX:DMA_CHANNEL_4
);
// TODO: Probably need to create other type for tx_dr and rx_dr
#[cfg(any(
feature = "gpio-f410",
feature = "gpio-f412",
Expand Down Expand Up @@ -402,7 +394,7 @@ mod dfsdm1 {
use pac::DFSDM as DFSDM1;
#[cfg(feature = "gpio-f413")]
use pac::DFSDM1;

dma_map!(
(Stream0<DMA2>:7, FLT<DFSDM1, 0>, [PeripheralToMemory]), //DFSDM1_FLT0
(Stream1<DMA2>:3, FLT<DFSDM1, 1>, [PeripheralToMemory]), //DFSDM1_FLT1
Expand Down Expand Up @@ -432,7 +424,7 @@ dma_map!(
(Stream7<DMA2>:8, FLT<pac::DFSDM2, 3>, [PeripheralToMemory]), //DFSDM2_FLT3
);
#[cfg(feature = "dfsdm2")]
unsafe impl<const F: u8> PeriAddress for CCR<DFSDM2, F> {
unsafe impl<const F: u8> PeriAddress for CCR<pac::DFSDM2, F> {

Check failure on line 427 in src/dma/traits/f4.rs

View workflow job for this annotation

GitHub Actions / ci (stm32f423, stable) 

cannot find type `CCR` in this scope
#[inline(always)]
fn address(&self) -> u32 {
unsafe { &(*DFSDM2::ptr()).flt[F as usize].rdatar as *const _ as u32 }

Check failure on line 430 in src/dma/traits/f4.rs

View workflow job for this annotation

GitHub Actions / ci (stm32f423, stable) 

failed to resolve: use of undeclared type `DFSDM2`
Expand Down Expand Up @@ -491,30 +483,31 @@ address!(
(pac::UART10, dr, u8),
);

/* Not sure how SAI works
#[cfg(any(
feature = "gpio-f413",
feature = "gpio-f427",
feature = "gpio-f446",
feature = "gpio-f469",
))]
dma_map!(
(Stream1<DMA2>:0, pac::SAI, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_A
(Stream3<DMA2>:0, pac::SAI, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_A
(Stream4<DMA2>:1, pac::SAI, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_B
(Stream5<DMA2>:0, pac::SAI, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_B:DMA_CHANNEL_0
);
#[cfg(feature = "sai1")]
mod sai1 {
use super::*;
#[cfg(not(feature = "gpio-f446"))]
use pac::SAI as SAI1;

Check failure on line 490 in src/dma/traits/f4.rs

View workflow job for this annotation

GitHub Actions / ci (stm32f427, stable) 

unresolved import `pac::SAI`

Check failure on line 490 in src/dma/traits/f4.rs

View workflow job for this annotation

GitHub Actions / ci (stm32f437, stable) 

unresolved import `pac::SAI`
#[cfg(feature = "gpio-f446")]
use pac::SAI1;

#[cfg(any(
feature = "gpio-f413",
feature = "gpio-f427",
feature = "gpio-f446",
feature = "gpio-f469",
))]
address!(
(pac::SAI, dr),
);
*/
dma_map!(
(Stream1<DMA2>:0, SAICH<SAI1, 0>, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_A
(Stream3<DMA2>:0, SAICH<SAI1, 0>, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_A
(Stream4<DMA2>:1, SAICH<SAI1, 1>, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_B
(Stream5<DMA2>:0, SAICH<SAI1, 1>, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_B:DMA_CHANNEL_0
);

#[cfg(feature = "sai1")]
unsafe impl<const C: u8> PeriAddress for SAICH<SAI1, C> {
#[inline(always)]
fn address(&self) -> u32 {
unsafe { &(*SAI1::ptr()).ch[C as usize].dr as *const _ as u32 }
}

type MemSize = u32;
}
}

#[cfg(any(feature = "gpio-f427", feature = "gpio-f469",))]
dma_map!(
Expand All @@ -534,16 +527,30 @@ dma_map!(
(Stream2<DMA1>:2, pac::FMPI2C1, [PeripheralToMemory]), //FMPI2C1_RX
(Stream5<DMA1>:2, pac::FMPI2C1, [MemoryToPeripheral]), //FMPI2C1_TX
(Stream6<DMA1>:0, pac::SPDIFRX, [PeripheralToMemory]), //SPDIF_RX_CS
(Stream4<DMA2>:3, pac::SAI2, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_A
(Stream6<DMA2>:3, pac::SAI2, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_B
(Stream7<DMA2>:0, pac::SAI2, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_B:DMA_CHANNEL_0
);
#[cfg(any(
feature = "gpio-f446",
))]
address!(
(pac::SPDIFRX, ??),
(pac::FMPI2C1, ??),
(pac::SAI2, ??),
);
*/

#[cfg(feature = "sai2")]
dma_map!(
(Stream4<DMA2>:3, SAICH<pac::SAI2, 0>, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_A
(Stream6<DMA2>:3, SAICH<pac::SAI2, 1>, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_B
(Stream7<DMA2>:0, SAICH<pac::SAI2, 1>, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_B:DMA_CHANNEL_0
);

#[cfg(feature = "sai2")]
unsafe impl<const C: u8> PeriAddress for SAICH<pac::SAI2, C> {
#[inline(always)]
fn address(&self) -> u32 {
unsafe { &(*pac::SAI2::ptr()).ch[C as usize].dr as *const _ as u32 }
}

type MemSize = u32;
}

0 comments on commit 388ba83

Please sign in to comment.