f7dma

stm32-rs · May 4, 2023 · cb80779 · cb80779
1 parent b5f8ac2
commit cb80779
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Showing 6 changed files with 450 additions and 300 deletions.
diff --git a/Cargo.toml b/Cargo.toml
@@ -616,6 +616,8 @@ dma = []
 uart_v1 = []
 uart_v2 = []
 usb_hs_phy = []
+dfsdm = []
+sai = []
 
 adc2 = []
 adc3 = []
@@ -636,7 +638,6 @@ crs = []
 dac = []
 dcmi = []
 debug = []
-dfsdm = []
 dfsdm1 = ["dfsdm"]
 dfsdm2 = ["dfsdm"]
 dsihost = []
@@ -694,8 +695,8 @@ pwr = []
 rf = []
 rng = []
 rtc = []
-sai1 = []
-sai2 = []
+sai1 = ["sai"]
+sai2 = ["sai"]
 sai3 = []
 sai4 = []
 sdio = []

diff --git a/src/dma/traits.rs b/src/dma/traits.rs
@@ -257,12 +257,11 @@ pub trait Channel {}
 pub unsafe trait DMASet<STREAM, const CHANNEL: u8, DIRECTION> {}
 
 macro_rules! dma_map {
-    ($(($Stream:ty:$C:literal, $Peripheral:ty, $Dir:ty $(|$Dir2:ty)?)),+ $(,)*) => {
+    ($(($Stream:ty:$C:literal, $Peripheral:ty, [$($Dir:ty)|+])),+ $(,)*) => {
         $(
-            unsafe impl DMASet<$Stream, $C, $Dir> for $Peripheral {}
             $(
-               unsafe impl DMASet<$Stream, $C, $Dir2> for $Peripheral {}
-            )?
+               unsafe impl DMASet<$Stream, $C, $Dir> for $Peripheral {}
+            )+
         )+
     };
 }
@@ -354,3 +353,30 @@ mod wb;
 #[cfg(feature = "wb")]
 pub use wb::*;
 */
+
+#[cfg(feature = "dfsdm")]
+pub struct FLT<T, const F: u8> {
+    _per: PhantomData<T>,
+}
+
+#[cfg(feature = "dfsdm")]
+impl<T, const F: u8> crate::Sealed for FLT<T, F> {}
+
+#[cfg(feature = "sai")]
+pub struct SAICH<T, const C: u8> {
+    _per: PhantomData<T>,
+}
+
+#[cfg(feature = "sai")]
+impl<T, const C: u8> crate::Sealed for SAICH<T, C> {}
+
+dma_map!(
+    (Stream0<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
+    (Stream1<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
+    (Stream2<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
+    (Stream3<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
+    (Stream4<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
+    (Stream5<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
+    (Stream6<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
+    (Stream7<DMA2>:0, MemoryToMemory<u8>, [MemoryToMemory<u8> | MemoryToMemory<u16> | MemoryToMemory<u32>]),
+);