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f2 dma
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@burrbull
burrbull committed May 6, 2023
1 parent 2ef7043 commit d2f80d9
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Showing 5 changed files with 336 additions and 3 deletions.
4 changes: 2 additions & 2 deletions src/dma/traits.rs
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Expand Up @@ -302,12 +302,12 @@ pub use f7::*;
mod g0;
#[cfg(feature = "g0")]
pub use g0::*;
*/
#[cfg(feature = "g4")]
mod g4;
#[cfg(feature = "g4")]
pub use g4::*;
/*
#[cfg(feature = "h7")]
mod h7;
#[cfg(feature = "h7")]
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93 changes: 93 additions & 0 deletions src/dma/traits/f2.rs
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use super::*;

dma_map! {
(Stream0<DMA1>:0, SPI3_RX, [PeripheralToMemory]), //SPI3_RX
(Stream2<DMA1>:0, SPI3_RX, [PeripheralToMemory]), //SPI3_RX
(Stream3<DMA1>:0, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
(Stream4<DMA1>:0, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
(Stream5<DMA1>:0, SPI3_TX, [MemoryToPeripheral]), //SPI3_TX
(Stream7<DMA1>:0, SPI3_TX, [MemoryToPeripheral]), //SPI3_TX
(Stream0<DMA1>:1, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
(Stream2<DMA1>:1, TIM7_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP
(Stream4<DMA1>:1, TIM7_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP
(Stream5<DMA1>:1, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
(Stream6<DMA1>:1, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
(Stream7<DMA1>:1, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
(Stream0<DMA1>:2, TIM4_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH1
(Stream3<DMA1>:2, TIM4_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH2
(Stream6<DMA1>:2, TIM4_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_UP
(Stream7<DMA1>:2, TIM4_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH3
(Stream1<DMA1>:3, TIM2_UP/CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP/CH3
(Stream2<DMA1>:3, I2C3_RX, [PeripheralToMemory]), //I2C3_RX
(Stream4<DMA1>:3, I2C3_TX, [MemoryToPeripheral]), //I2C3_TX
(Stream5<DMA1>:3, TIM2_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
(Stream6<DMA1>:3, TIM2_CH2/CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2/CH4
(Stream7<DMA1>:3, TIM2_UP/CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP/CH4
(Stream0<DMA1>:4, UART5_RX, [PeripheralToMemory]), //UART5_RX
(Stream1<DMA1>:4, USART3_RX, [PeripheralToMemory]), //USART3_RX
(Stream2<DMA1>:4, UART4_RX, [PeripheralToMemory]), //UART4_RX
(Stream3<DMA1>:4, USART3_TX, [MemoryToPeripheral]), //USART3_TX
(Stream4<DMA1>:4, UART4_TX, [MemoryToPeripheral]), //UART4_TX
(Stream5<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
(Stream6<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
(Stream7<DMA1>:4, UART5_TX, [MemoryToPeripheral]), //UART5_TX
(Stream2<DMA1>:5, TIM3_CH4/UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4/UP
(Stream4<DMA1>:5, TIM3_CH1/TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1/TRIG
(Stream5<DMA1>:5, TIM3_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH2
(Stream7<DMA1>:5, TIM3_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3
(Stream0<DMA1>:6, TIM5_CH3/UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH3/UP
(Stream1<DMA1>:6, TIM5_CH4/TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4/TRIG
(Stream2<DMA1>:6, TIM5_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH1
(Stream3<DMA1>:6, TIM5_CH4/TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4/TRIG
(Stream4<DMA1>:6, TIM5_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH2
(Stream6<DMA1>:6, TIM5_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP
(Stream1<DMA1>:7, TIM6_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP
(Stream2<DMA1>:7, I2C2_RX, [PeripheralToMemory]), //I2C2_RX
(Stream3<DMA1>:7, I2C2_RX, [PeripheralToMemory]), //I2C2_RX
(Stream4<DMA1>:7, USART3_TX:DMA_CHANNEL_7, [MemoryToPeripheral]), //USART3_TX:DMA_CHANNEL_7
(Stream5<DMA1>:7, DAC1, [MemoryToPeripheral]), //DAC1
(Stream6<DMA1>:7, DAC2, [MemoryToPeripheral]), //DAC2
(Stream7<DMA1>:7, I2C2_TX, [MemoryToPeripheral]), //I2C2_TX
(Stream0<DMA2>:0, ADC1, [PeripheralToMemory]), //ADC1
(Stream2<DMA2>:0, TIM8_CH1/CH2/CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1/CH2/CH3
(Stream4<DMA2>:0, ADC1, [PeripheralToMemory]), //ADC1
(Stream6<DMA2>:0, TIM1_CH1/CH2/CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1/CH2/CH3
(Stream1<DMA2>:1, DCMI, [PeripheralToMemory]), //DCMI
(Stream2<DMA2>:1, ADC2, [PeripheralToMemory]), //ADC2
(Stream3<DMA2>:1, ADC2, [PeripheralToMemory]), //ADC2
(Stream7<DMA2>:1, DCMI, [PeripheralToMemory]), //DCMI
(Stream0<DMA2>:2, ADC3, [PeripheralToMemory]), //ADC3
(Stream1<DMA2>:2, ADC3, [PeripheralToMemory]), //ADC3
(Stream5<DMA2>:2, CRYP_OUT, [PeripheralToMemory]), //CRYP_OUT
(Stream6<DMA2>:2, CRYP_IN, [MemoryToPeripheral]), //CRYP_IN
(Stream7<DMA2>:2, HASH_IN, [MemoryToPeripheral]), //HASH_IN
(Stream0<DMA2>:3, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
(Stream2<DMA2>:3, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
(Stream3<DMA2>:3, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
(Stream5<DMA2>:3, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
(Stream2<DMA2>:4, USART1_RX, [PeripheralToMemory]), //USART1_RX
(Stream3<DMA2>:4, SDIO:Conflict:SDIO_RX,SDIO_TX, [MemoryToPeripheral | PeripheralToMemory]), //SDIO:Conflict:SDIO_RX,SDIO_TX
(Stream3<DMA2>:4, SDIO_RX:Conflict:SDIO, [PeripheralToMemory]), //SDIO_RX:Conflict:SDIO
(Stream3<DMA2>:4, SDIO_TX:Conflict:SDIO, [MemoryToPeripheral]), //SDIO_TX:Conflict:SDIO
(Stream5<DMA2>:4, USART1_RX, [PeripheralToMemory]), //USART1_RX
(Stream6<DMA2>:4, SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO
(Stream6<DMA2>:4, SDIO_RX, [PeripheralToMemory]), //SDIO_RX
(Stream6<DMA2>:4, SDIO_TX, [MemoryToPeripheral]), //SDIO_TX
(Stream7<DMA2>:4, USART1_TX, [MemoryToPeripheral]), //USART1_TX
(Stream1<DMA2>:5, USART6_RX, [PeripheralToMemory]), //USART6_RX
(Stream2<DMA2>:5, USART6_RX, [PeripheralToMemory]), //USART6_RX
(Stream6<DMA2>:5, USART6_TX, [MemoryToPeripheral]), //USART6_TX
(Stream7<DMA2>:5, USART6_TX, [MemoryToPeripheral]), //USART6_TX
(Stream0<DMA2>:6, TIM1_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG
(Stream1<DMA2>:6, TIM1_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
(Stream2<DMA2>:6, TIM1_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2
(Stream3<DMA2>:6, TIM1_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
(Stream4<DMA2>:6, TIM1_CH4/TRIG/COM, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH4/TRIG/COM
(Stream5<DMA2>:6, TIM1_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_UP
(Stream6<DMA2>:6, TIM1_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3
(Stream1<DMA2>:7, TIM8_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_UP
(Stream2<DMA2>:7, TIM8_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1
(Stream3<DMA2>:7, TIM8_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH2
(Stream4<DMA2>:7, TIM8_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH3
(Stream7<DMA2>:7, TIM8_CH4/TRIG/COM, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH4/TRIG/COM
}
1 change: 0 additions & 1 deletion src/dma/traits/g4.rs
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This file was deleted.

133 changes: 133 additions & 0 deletions src/dma/traits/l0.rs
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use super::*;

#[cfg(feature = "STM32L021_dma_v1_1")]
dma_map! {
(Channel1<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
(Channel2<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
(Channel4<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
(Channel2<DMA1>:1, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
(Channel3<DMA1>:1, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
(Channel4<DMA1>:1, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
(Channel5<DMA1>:1, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
(Channel2<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
(Channel3<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
(Channel4<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
(Channel5<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
(Channel2<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
(Channel3<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
(Channel4<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
(Channel5<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
(Channel2<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
(Channel3<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
(Channel4<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
(Channel5<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
(Channel1<DMA1>:8, TIM2_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3
(Channel2<DMA1>:8, TIM2_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP
(Channel3<DMA1>:8, TIM2_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
(Channel4<DMA1>:8, TIM2_CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
(Channel5<DMA1>:8, TIM2_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
(Channel1<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
(Channel2<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
(Channel3<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
(Channel5<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
}
#[cfg(feature = "STM32L063_dma_v1_1")]
dma_map! {
(Channel1<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
(Channel2<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
(Channel2<DMA1>:1, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
(Channel3<DMA1>:1, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
(Channel4<DMA1>:2, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
(Channel5<DMA1>:2, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
(Channel6<DMA1>:2, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
(Channel7<DMA1>:2, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
(Channel2<DMA1>:3, USART1_TX, [MemoryToPeripheral]), //USART1_TX
(Channel3<DMA1>:3, USART1_RX, [PeripheralToMemory]), //USART1_RX
(Channel4<DMA1>:3, USART1_TX, [MemoryToPeripheral]), //USART1_TX
(Channel5<DMA1>:3, USART1_RX, [PeripheralToMemory]), //USART1_RX
(Channel4<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
(Channel5<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
(Channel6<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
(Channel7<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
(Channel2<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
(Channel3<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
(Channel6<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
(Channel7<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
(Channel2<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
(Channel3<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
(Channel6<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
(Channel7<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
(Channel4<DMA1>:7, I2C2_TX, [MemoryToPeripheral]), //I2C2_TX
(Channel5<DMA1>:7, I2C2_RX, [PeripheralToMemory]), //I2C2_RX
(Channel1<DMA1>:8, TIM2_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3
(Channel2<DMA1>:8, TIM2_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP
(Channel3<DMA1>:8, TIM2_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
(Channel4<DMA1>:8, TIM2_CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
(Channel5<DMA1>:8, TIM2_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
(Channel7<DMA1>:8, TIM2_CH2/CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2/CH4
(Channel2<DMA1>:9, DAC_CH1, [MemoryToPeripheral]), //DAC_CH1
(Channel2<DMA1>:9, TIM6_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP
(Channel1<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
(Channel2<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
(Channel3<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
(Channel5<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
}
#[cfg(feature = "STM32L083_dma_v1_1")]
dma_map! {
(Channel1<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
(Channel2<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
(Channel2<DMA1>:1, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
(Channel3<DMA1>:1, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
(Channel4<DMA1>:2, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
(Channel5<DMA1>:2, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
(Channel6<DMA1>:2, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
(Channel7<DMA1>:2, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
(Channel2<DMA1>:3, USART1_TX, [MemoryToPeripheral]), //USART1_TX
(Channel3<DMA1>:3, USART1_RX, [PeripheralToMemory]), //USART1_RX
(Channel4<DMA1>:3, USART1_TX, [MemoryToPeripheral]), //USART1_TX
(Channel5<DMA1>:3, USART1_RX, [PeripheralToMemory]), //USART1_RX
(Channel4<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
(Channel5<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
(Channel6<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
(Channel7<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
(Channel2<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
(Channel3<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
(Channel6<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
(Channel7<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
(Channel2<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
(Channel3<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
(Channel6<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
(Channel7<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
(Channel4<DMA1>:7, I2C2_TX, [MemoryToPeripheral]), //I2C2_TX
(Channel5<DMA1>:7, I2C2_RX, [PeripheralToMemory]), //I2C2_RX
(Channel1<DMA1>:8, TIM2_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3
(Channel2<DMA1>:8, TIM2_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP
(Channel3<DMA1>:8, TIM2_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
(Channel4<DMA1>:8, TIM2_CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
(Channel5<DMA1>:8, TIM2_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
(Channel7<DMA1>:8, TIM2_CH2/CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2/CH4
(Channel2<DMA1>:9, DAC_CH1, [MemoryToPeripheral]), //DAC_CH1
(Channel2<DMA1>:9, TIM6_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP
(Channel2<DMA1>:10, TIM3_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3
(Channel3<DMA1>:10, TIM3_CH4/UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4/UP
(Channel5<DMA1>:10, TIM3_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1
(Channel6<DMA1>:10, TIM3_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_TRIG
(Channel1<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
(Channel2<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
(Channel3<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
(Channel5<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
(Channel2<DMA1>:12, USART4_RX, [PeripheralToMemory]), //USART4_RX
(Channel3<DMA1>:12, USART4_TX, [MemoryToPeripheral]), //USART4_TX
(Channel6<DMA1>:12, USART4_RX, [PeripheralToMemory]), //USART4_RX
(Channel7<DMA1>:12, USART4_TX, [MemoryToPeripheral]), //USART4_TX
(Channel2<DMA1>:13, USART5_RX, [PeripheralToMemory]), //USART5_RX
(Channel3<DMA1>:13, USART5_TX, [MemoryToPeripheral]), //USART5_TX
(Channel6<DMA1>:13, USART5_RX, [PeripheralToMemory]), //USART5_RX
(Channel7<DMA1>:13, USART5_TX, [MemoryToPeripheral]), //USART5_TX
(Channel2<DMA1>:14, I2C3_TX, [MemoryToPeripheral]), //I2C3_TX
(Channel3<DMA1>:14, I2C3_RX, [PeripheralToMemory]), //I2C3_RX
(Channel4<DMA1>:14, I2C3_TX, [MemoryToPeripheral]), //I2C3_TX
(Channel5<DMA1>:14, I2C3_RX, [PeripheralToMemory]), //I2C3_RX
(Channel4<DMA1>:15, DAC_CH2, [MemoryToPeripheral]), //DAC_CH2
(Channel4<DMA1>:15, TIM7_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP
}
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