Fast double-buffered DMA #226
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Currently there is 2 PCLK delay (equivalent to up to 8 CPU cycles) when clearing transfer complete flags for the update to trickle through the bus matrices, the peripheral and the irq synchronizer after clearing an interrupt flag. In many cases the delay is not required because there are enough instruction following before exiting an ISR that would fully absorb the delay. This change adds a method to clear the flag without additional delay.
This add a new unsafe method to the DMA API for significantly faster transfer handling. In many cases the safety and universality offered by `next_transfer_with` is not necessary and costly in terms of cycles. This is especially the case when multiple double-buffer DMA streams are handled together and when the risk of loosing the race to the inactive buffer against the running DMA transfer is either acceptable or excluded by design of the handler.
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It's really interesting that such a dramatic speedup is possible. I guess that's with release mode / optimisations enabled in both cases? The PR looks good to me. |
Even without address poisoning and buffer swapping we can detect the case where the user processing is too slow and DMA wins the race to the inactive buffer. This returns `Err(DMAError::Overflow)` in that case at the small expense of a single additional peripheral read.
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Yes. That's always in |
richardeoin
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Jun 7, 2021
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Thanks! bors r+ |
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When handling multiple double-buffered DMA streams the current safe-and-universal API becomes slower than necessary.
This adds
next_dbm_transfer_with(), a closure-based API to the inactive buffer, without address poisoning, compiler fences, data barriers, or buffer swapping. For some applications this reduces the overhead significantly (speedup of 5).