Merge pull request #105 from stnolting/dev1205

plugin updates and fixes

plugin-neorv32/neorv32_isa.yaml

@@ -1,5 +1,4 @@
 hart_ids: [0]
-mtval_update: 0b11110011
 hart0:
   ISA: RV32IMCUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 32

plugin-neorv32/neorv32_platform.yaml

@@ -8,13 +8,3 @@ nmi:
   label: nmi_vector
 reset:
   address: 0x00000000
-mtval_condition_writes:
-  implemented: true
-  behaviour:
-    e00: "[0x00000000:0x00000000], 'Instruction fetch - address that was misaligned'"
-    e01: "[0x00000000:0x00000000], 'Instruction fetch - address that triggered a bus exception'"
-    e03: "[0x00000000:0x00000000], 'Breakpoint - set to zero'"
-    e04: "[0x00000000:0x00000000], 'Load access - address that was misaligned'"
-    e05: "[0x00000000:0x00000000], 'Load access - address that triggered a bus exception'"
-    e06: "[0x00000000:0x00000000], 'Store access - address that was misaligned'"
-    e07: "[0x00000000:0x00000000], 'Store access - address that triggered a bus exception'"

plugin-neorv32/riscof_neorv32.py

@@ -173,18 +173,14 @@ def runTests(self, testList):
 
           # prepare run of GHDL simulation
           execute = 'sh ./sim/ghdl_run.sh'
-          # set TB generics according to MARCH test case
-          if "e" in marchstr:
-              execute += ' -gRISCV_E=true'
-          if "m" in marchstr:
+          # override testbench generics according to MARCH test case
+          if "rv32im" in marchstr:
               execute += ' -gRISCV_M=true'
           # 'privilege' tests also require C extension
-          if "c" in marchstr or "privilege" in test:
+          if "rv32ic" in marchstr or "privilege" in test:
               execute += ' -gRISCV_C=true'
-          if "b" in marchstr:
+          if "rv32izba" in marchstr or "rv32izbb" in marchstr or "rv32izbc" in marchstr or "rv32izbs" in marchstr:
               execute += ' -gRISCV_B=true'
-          if "u" in marchstr:
-              execute += ' -gRISCV_U=true'
           logger.debug('DUT executing ' + execute)
           utils.shellCommand(execute).run()
 

sim/neorv32_riscof_tb.vhd

@@ -61,8 +61,7 @@ entity neorv32_riscof_tb is
     RISCV_B   : boolean := false; -- bit-manipulation ISA extension
     RISCV_C   : boolean := false; -- compressed ISA extension
     RISCV_E   : boolean := false; -- embedded ISA extension
-    RISCV_M   : boolean := false; -- hardware mul/div ISA extension
-    RISCV_U   : boolean := false  -- user-mode ISA extension
+    RISCV_M   : boolean := false  -- hardware mul/div ISA extension
   );
 end neorv32_riscof_tb;
 
@@ -142,7 +141,7 @@ begin
     CPU_EXTENSION_RISCV_C        => RISCV_C,
     CPU_EXTENSION_RISCV_E        => RISCV_E,
     CPU_EXTENSION_RISCV_M        => RISCV_M,
-    CPU_EXTENSION_RISCV_U        => RISCV_U,
+    CPU_EXTENSION_RISCV_U        => true,
     CPU_EXTENSION_RISCV_Zicntr   => true,
     CPU_EXTENSION_RISCV_Zifencei => true,
     -- Extension Options --