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馃悰 WFI instruction with global interrupts disabled #583

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stnolting opened this issue Apr 15, 2023 Discussed in #582 · 0 comments 路 Fixed by #586
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馃悰 WFI instruction with global interrupts disabled #583

stnolting opened this issue Apr 15, 2023 Discussed in #582 · 0 comments 路 Fixed by #586
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bug Something isn't working HW hardware-related risc-v compliance Modification to comply with official RISC-V specs.

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Discussed in #582

Originally posted by biosbob April 14, 2023
the risc-v instruction set manual states that WFI can be executed with global interrupts disabled.... the neorv32 datasheet, however, requires that global interrupt flag in the mstatus register has to be set....

when implemented a task scheduler (as i am), the kernel will typically disable global interrupts which (atomically) manipulating its internal data structures.... if no task is ready to run, the kernel will "idle" by executing WFI....

other CPUs (eg., Arm) will define the WFI instruction to enable global interrupts before waiting -- or else returning immediately if some interrupt is already pending.... the point here is that this is all happening atomically; there is no window of vulerability between enabling global interrupts and executing WFI....

in the case of the risc-v WFI, our kernel would executing this instruction with interrupts disabled.... as per the spec, the PC will advance to the next instruction once some interrupt if pending.... in my implementation, i'll conditionally enable global interrupts if mip is non-zero; the ISR(s) will then execute on mstatus has been written....

i suspect this is a trivial change to the RTL; and it certainly wouldn't impact any of the software examples, as this new implementation is more permissive....

but am i missing something????

@stnolting stnolting added bug Something isn't working risc-v compliance Modification to comply with official RISC-V specs. labels Apr 15, 2023
@stnolting stnolting self-assigned this Apr 15, 2023
@stnolting stnolting added the HW hardware-related label Apr 15, 2023
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bug Something isn't working HW hardware-related risc-v compliance Modification to comply with official RISC-V specs.
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