The NEORV32 RISC-V Processor
- FPGA Implementation Results
- Software Framework & Tooling
- Getting Started
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the NEORV32 RISC-V CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power and low-density FPGA running at +24 MHz.
Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.
- all-in-one package: CPU + SoC + Software Framework & Tooling
- completely described in behavioral, platform-independent VHDL - no platform-specific primitives, macros, attributes, etc.
- extensive configuration options for adapting the processor to the requirements of the application
- highly extensible hardware - on CPU, processor and system level
- aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
- FPGA friendly (e.g. all internal memories can be mapped to block RAM - including the register file)
- optimized for high clock frequencies to ease timing closure and integration
- from zero to "hello world!" - completely open source and documented
- easy to use even for FPGA / RISC-V starters – intended to work out of the box
The NEORV32 is fully operational.
The processor passes the official RISC-V architecture tests, which is checked by the
neorv32-verif repository. It can successfully run any C program
(for example from the
sw/example folder) including CoreMark
and FreeRTOS and can be synthesized for any target technology - tested on Intel, Xilinx and Lattice FPGAs.
The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. By using generics the design is highly configurable and allows a flexible customization to tailor the setup according to your needs. Note that all of the following SoC modules are entirely optional.
- 32-bit little-endian RISC-V single-core, pipelined/multi-cycle modified Harvard architecture
- configurable ISA extensions:
- compatible to subsets of the RISC-V Unprivileged ISA Specification (pdf) and Privileged Architecture Specification (pdf).
- implements all standard RISC-V exceptions and interrupts (including MTI, MEI & MSI)
- 16 fast interrupt request channels as NEORV32-specific extension
- processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
- pre-installed bootloader (BOOTLDROM) with serial user interface; allows booting application code via UART or from external SPI flash
- 64-bit machine system timer (MTIME), RISC-V spec. compatible
- 32-bit general purpose timer (GPTMR)
- watchdog timer (WDT)
Input / Output
- standard serial interfaces (UART, SPI, TWI)
- general purpose IOs (GPIO) and PWM
- smart LED interface (NEOLED) to directly control NeoPixel(TM) LEDs
- 32-bit external bus interface - Wishbone b4 compatible (WISHBONE); wrappers for AXI4-Lite and Avalon-MM host interfaces
- 32-bit stream link interface with up to 8 independent RX and TX channels (SLINK) - AXI4-Stream compatible
- external interrupts controller with up to 32 channels (XIRQ)
- true random number generator (TRNG) based on the neoTRNG
- execute-in-place module (XIP) to execute code directly from SPI flash
- custom functions subsystem (CFS) for custom tightly-coupled co-processors, accelerators or interfaces
- custom functions unit (CFU) for up to 1024 custom RISC-V instructions
- on-chip debugger (OCD) accessible via standard JTAG interface
- compliant to the "Minimal RISC-V Debug Specification Version 0.13.2"
- compatible with OpenOCD + gdb and Segger Embedded Studio
Zmmul RISC-V ISA extensions are frozen and officially ratified but there is no
upstream gcc support yet (will be available with GCC12). To circumvent this, the NEORV32 software framework provides
intrinsic libraries for the
3. FPGA Implementation Results
Implementation results for exemplary CPU configurations generated for an Intel Cyclone IV
using Intel Quartus Prime Lite 21.1 (no timing constrains, balanced optimization, f_max from Slow 1200mV 0C Model).
|CPU Configuration (version 22.214.171.124)||LEs||FFs||Memory bits||DSPs||f_max|
neorv32-setups repository provides exemplary FPGA
setups targeting various FPGA boards and toolchains.
The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.
The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing 2000 iterations of the CoreMark CPU benchmark (using plain GCC10 rv32i built-in libraries only!).
|CPU Configuration (version 126.96.36.199)||CoreMark Score||CoreMarks/MHz||Average CPI|
5. Software Framework and Tooling
- core libraries for high-level usage of the provided functions and peripherals
- application compilation based on GNU makefiles
- gcc-based toolchain (pre-compiled toolchains available)
- SVD file for advanced debugging and IDE integration
- bootloader with UART interface console
- runtime environment for handling traps
- several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
- doxygen-based documentation, available on GitHub pages
- supports implementation using open source toolchains - both, software and hardware can be developed and debugged with open source tools (GHDL, Yosys, nextpnr, openOCD, gtkwave, ...)
- continuous integration is available for:
6. Getting Started
- Rationale - NEORV32: Why? How come? What for?
🔌 Hardware Overview
NEORV32 Processor - the SoC
NEORV32 CPU - the CPU
💾 Software Overview
- Example Programs - examples how to use the processor's IO/peripheral modules
- Core Libraries - high-level functions for accessing the processor's peripherals
- Software Framework Documentation - doxygen-based
- Application Makefile - turning your application into an executable
- Bootloader - the build-in NEORV32 bootloader
🚀 User Guide
- Toolchain Setup - install and setup the RISC-V GCC toolchain
- General Hardware Setup - setup a new NEORV32 FPGA project
- General Software Setup - configure the software framework
- Application Compilation - compile an application using
- Upload via Bootloader - upload and execute executables
- Application-Specific Processor Configuration - tailor the processor to your needs
- Adding Custom Hardware Modules - add your custom hardware
- Debugging via the On-Chip Debugger - step through code online and in-system
- Simulation - simulate the whole SoC
- LiteX Integration - build a SoC using NEORV32 + LiteX
- Overview - license, disclaimer, limitation of liability for external links, proprietary notice, etc.
- Citing - citing information
This is an open-source project that is free of charge. Use this project in any way you like
(as long as it complies to the permissive license).
Please cite it appropriately.