Skip to content


Switch branches/tags

Latest commit

Functions/lables do not need to be 32-bit-aligned (if C extension is enabled) to increase instruction fetch - thanks to the reworked CPU front-end from v1.7.0.3.

Git stats


Failed to load latest commit information.


The NEORV32 RISC-V Processor

datasheet (pdf) datasheet (html) userguide (pdf) userguide (html) doxygen Gitter

  1. Overview
  2. Features
  3. FPGA Implementation Results
  4. Performance
  5. Software Framework & Tooling
  6. Getting Started 🚀

1. Overview

neorv32 Overview

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the NEORV32 RISC-V CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power and low-density FPGA running at +24 MHz.

Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.

⁉️ Want to know more? Check out the project's rationale.

📚 For detailed information take a look at the NEORV32 online documentation. The latest PDF versions can be found here.

🏷️ The project's change log is available in To see the changes between official releases visit the project's release page.

📦 Exemplary setups targeting various FPGA boards and toolchains to get you started. Also check out the list of community projects there.

✔️ Automatic check for RISC-V specification compliance.

🪁 Support for Zephyr & FreeRTOS operating systems and LiteX SoC Builder Framework.

💡 Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or if something is not working as expected. Or have a chat on our gitter channel. See how to contribute.

🚀 Check out the quick links below or directly jump to the User Guide to get started setting up your NEORV32 setup!

Key Features

  • all-in-one package: CPU + SoC + Software Framework & Tooling
  • completely described in behavioral, platform-independent VHDL - no platform-specific primitives, macros, attributes, etc.
  • extensive configuration options for adapting the processor to the requirements of the application
  • highly extensible hardware - on CPU, processor and system level
  • aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
  • FPGA friendly (e.g. all internal memories can be mapped to block RAM - including the register file)
  • optimized for high clock frequencies to ease timing closure and integration
  • from zero to "hello world!" - completely open source and documented
  • easy to use even for FPGA / RISC-V starters – intended to work out of the box


release GitHub Pages
Documentation Processor riscv-arch-test Implementation

The NEORV32 is fully operational. The processor passes the official RISC-V architecture tests, which is checked by the neorv32-verif repository. It can successfully run any C program (for example from the sw/example folder) including CoreMark and FreeRTOS and can be synthesized for any target technology - tested on Intel, Xilinx and Lattice FPGAs.

[back to top]

2. Features

The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. By using generics the design is highly configurable and allows a flexible customization to tailor the setup according to your needs. Note that all of the following SoC modules are entirely optional.

CPU Core

  • 32-bit little-endian RISC-V single-core, pipelined/multi-cycle modified Harvard architecture
  • configurable ISA extensions:
    RV32 [I/ E] [B] [C] [M] [U] [X] [Zfinx] [Zicsr] [Zicntr] [Zihpm] [Zifencei] [Zmmul] [Zxcfu] [PMP] [DEBUG]
  • compatible to subsets of the RISC-V Unprivileged ISA Specification (pdf) and Privileged Architecture Specification (pdf).
  • machine and user privilege modes
  • implements all standard RISC-V exceptions and interrupts (including MTI, MEI & MSI)
  • 16 fast interrupt request channels as NEORV32-specific extension


  • processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
  • pre-installed bootloader (BOOTLDROM) with serial user interface; allows booting application code via UART or from external SPI flash


  • 64-bit machine system timer (MTIME), RISC-V spec. compatible
  • 32-bit general purpose timer (GPTMR)
  • watchdog timer (WDT)

Input / Output

  • standard serial interfaces (UART, SPI, TWI)
  • general purpose IOs (GPIO) and PWM
  • smart LED interface (NEOLED) to directly control NeoPixel(TM) LEDs

SoC Connectivity

  • 32-bit external bus interface - Wishbone b4 compatible (WISHBONE); wrappers for AXI4-Lite and Avalon-MM host interfaces
  • 32-bit stream link interface with up to 8 independent RX and TX channels (SLINK) - AXI4-Stream compatible
  • external interrupts controller with up to 32 channels (XIRQ)


  • true random number generator (TRNG) based on the neoTRNG
  • execute-in-place module (XIP) to execute code directly from SPI flash
  • custom functions subsystem (CFS) for custom tightly-coupled co-processors, accelerators or interfaces
  • custom functions unit (CFU) for up to 1024 custom RISC-V instructions


  • on-chip debugger (OCD) accessible via standard JTAG interface
  • compliant to the "Minimal RISC-V Debug Specification Version 0.13.2"
  • compatible with OpenOCD + gdb and Segger Embedded Studio

⚠️ The B, Zfinx and Zmmul RISC-V ISA extensions are frozen and officially ratified but there is no upstream gcc support yet (will be available with GCC12). To circumvent this, the NEORV32 software framework provides intrinsic libraries for the B and Zfinx extensions.

[back to top]

3. FPGA Implementation Results

Implementation results for exemplary CPU configurations generated for an Intel Cyclone IV EP4CE22F17C6 FPGA using Intel Quartus Prime Lite 21.1 (no timing constrains, balanced optimization, f_max from Slow 1200mV 0C Model).

CPU Configuration (version LEs FFs Memory bits DSPs f_max
rv32i_Zicsr 1328 678 1024 0 128 MHz
rv32i_Zicsr_Zicntr 1614 808 1024 0 128 MHz
rv32imc_Zicsr_Zicntr 2338 992 1024 0 128 MHz

💡 An incremental list of the CPU extensions and the Processor modules found in the Data Sheet: FPGA Implementation Results.

💡 The neorv32-setups repository provides exemplary FPGA setups targeting various FPGA boards and toolchains.

[back to top]

4. Performance

The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.

The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing 2000 iterations of the CoreMark CPU benchmark (using plain GCC10 rv32i built-in libraries only!).

CPU Configuration (version CoreMark Score CoreMarks/MHz Average CPI
small (rv32i_Zicsr) 33.89 0.3389 4.04
medium (rv32imc_Zicsr) 62.50 0.6250 5.34
performance (rv32imc_Zicsr + perf. options) 95.23 0.9523 3.54

💡 More information regarding the CPU performance can be found in the Data Sheet: CPU Performance. The CPU & SoC provide further "tuning" options to optimize the design for maximum performance, maximum clock speed, minimal area or minimal power consumption: UG: Application-Specific Processor Configuration

[back to top]

5. Software Framework and Tooling

  • core libraries for high-level usage of the provided functions and peripherals
  • application compilation based on GNU makefiles
  • gcc-based toolchain (pre-compiled toolchains available)
  • SVD file for advanced debugging and IDE integration
  • bootloader with UART interface console
  • runtime environment for handling traps
  • several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
  • doxygen-based documentation, available on GitHub pages
  • supports implementation using open source toolchains - both, software and hardware can be developed and debugged with open source tools (GHDL, Yosys, nextpnr, openOCD, gtkwave, ...)
  • continuous integration is available for:

💡 Want to know more? Check out Data Sheet: Software Framework.

[back to top]

6. Getting Started

This overview provides some quick links to the most important sections of the online Data Sheet and the online User Guide.

⁉️ Rationale

  • Rationale - NEORV32: Why? How come? What for?

🔌 Hardware Overview

💾 Software Overview

🚀 User Guide

©️ Legal

license DOI

  • Overview - license, disclaimer, limitation of liability for external links, proprietary notice, etc.
  • Citing - citing information

This is an open-source project that is free of charge. Use this project in any way you like (as long as it complies to the permissive license). Please cite it appropriately. 👍

[back to top]

❤️ A big shout-out to the community and all the contributors, who helped improving this project!