Digital-Systems-Laboratory

Projects I made in Introduction to Microcomputers. I used Logisim for my projects.

Table of Contents

• Parity bit generator circuit
• Combinational logic circuit
• Half adder circuit
• Full adder circuit
• Adder or Subtractor circuit
  • IC 7483
• SR Latch
• D Latch
• Flip Flop 1
  • J-K Flip Flop
  • IC 7476
• Flip Flop 2
  • D Flip Flop
  • IC 7474
• Synchronous 4-bit counter
• Synchronous 4-bit counter with 7474
• BCD Counters
  • D Flip Flop
  • IC 7493
  • Count to 16
  • Count to 10
  • Count to 6
  • Count to 8
  • Count to 12

Parity bit generator circuit

with 4 line-to-1 line multiplexer and external gates.

It is combinational circuit that accepts an n-1 bit data and generates the additional bit that is to be transmitted with the bit stream. This additional or extra bit is called as a Parity Bit.

Combinational logic circuit

• If A+B is EVEN, Z1Z2=01

• If A+B is ODD, Z1Z2=10

with 3-to-8 line decoders and external logic gates.

Half adder circuit

using only XOR and NAND gates.

Half Adder is a combinational logic circuit which is designed by connecting one XOR gate and one NAND gate. The half adder circuit has two inputs: A and B, which add two input digits and generates a carry and a sum. The output obtained from the XOR gate is the sum of the two numbers while that obtained by NAND gate is the carry.

Output Example

Full adder circuit

using only XOR and NAND gates.

Full Adder is the circuit that consists of two XOR gates and three NAND gates. Full Adder is the adder that adds three inputs and produces two outputs which consist of two XOR gates and three NAND gates. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM. The equation obtained by the XOR gate is the sum of the binary digits. While the output obtained by NAND gate is the carry obtained by addition.

Output Example

Adder or Subtractor circuit

Implemented with IC 7483. The circuit uses signed 2’s complement system for negative numbers.

A Binary Adder-Subtractor is one that is capable of both the addition and subtraction of binary numbers in one circuit itself. The operation is performed depending on the binary value the control signal holds. It is one of the components of the ALU (Arithmetic Logic Unit).

Output Example

IC 7483

SR Latch

D Latch

A D Flip Flop (also known as a D Latch or a ‘data’ or ‘delay’ flip-flop) is a type of flip flop that tracks the input, making transitions with match those of the input D. The D stands for ‘data’, this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell.

Output Example

Flip Flop 1

Implemented with IC 7476.

Output Example

IC 7476

J-K Flip Flop

Flip Flop 2

Implemented with IC 7474.

Output Example

IC 7474

D Flip Flop

Synchronous 4-bit counter

A synchronous sequential circuit with one input x, and one output z. When x=1, this circuit goes through the following repeated binary state sequence: 00, 01, 11, 10. When x=0, the state of the circuit remains the same. The output z=1 if the present state is either 00 or 11.

Output Example

Synchronous 4-bit counter with 7474

The 7474 IC contains two independent positive-edge-triggered D flip-flops with complementary outputs.

BCD Counters

D Flip Flop

IC 7493

Count to 16

Count to 10

Count to 6

Count to 8

Count to 12