Skip to content

Commit

Permalink
[WIP] drm/meson: Support Overlay plane for video rendering
Browse files Browse the repository at this point in the history 
The Amlogic Meson GX SoCs support an Overlay plane behind the primary
plan for video rendering.
This Overlay plane support various YUV layouts and a non-alpha RGB32
layout.
  • Loading branch information
@superna9999
superna9999 committed Sep 10, 2018
1 parent 665dbad commit a428200
Show file tree
Hide file tree
Showing 10 changed files with 912 additions and 7 deletions.
2 changes: 1 addition & 1 deletion drivers/gpu/drm/meson/Makefile
View file
@@ -1,5 +1,5 @@
meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o
meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o
meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_overlay.o

obj-$(CONFIG_DRM_MESON) += meson-drm.o
obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
172 changes: 171 additions & 1 deletion drivers/gpu/drm/meson/meson_crtc.c
View file
Expand Up @@ -25,6 +25,7 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/bitfield.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
Expand Down Expand Up @@ -97,6 +98,10 @@ static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
writel(crtc_state->mode.hdisplay,
priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));

/* VD1 Preblend vertical start/end */
writel(FIELD_PREP(GENMASK(11, 0), 2303),
priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));

writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
priv->io_base + _REG(VPP_MISC));

Expand All @@ -109,11 +114,17 @@ static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
struct meson_drm *priv = meson_crtc->priv;

DRM_DEBUG_DRIVER("\n");

priv->viu.osd1_enabled = false;
priv->viu.osd1_commit = false;

priv->viu.vd1_enabled = false;
priv->viu.vd1_commit = false;

/* Disable VPP Postblend */
writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND |
VPP_VD1_PREBLEND | VPP_POSTBLEND_ENABLE, 0,
priv->io_base + _REG(VPP_MISC));

if (crtc->state->event && !crtc->state->active) {
Expand Down Expand Up @@ -148,6 +159,7 @@ static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
struct meson_drm *priv = meson_crtc->priv;

priv->viu.osd1_commit = true;
priv->viu.vd1_commit = true;
}

static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
Expand Down Expand Up @@ -204,6 +216,164 @@ void meson_crtc_irq(struct meson_drm *priv)
priv->viu.osd1_commit = false;
}

/* Update the VD1 registers */
if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {

switch (priv->viu.vd1_planes) {
case 3:
meson_canvas_config(priv->canvas, priv->canvas_id_vd1_2,
priv->viu.vd1_addr2, priv->viu.vd1_stride2,
priv->viu.vd1_height2, MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR, MESON_CANVAS_ENDIAN_SWAP64);
case 2:
meson_canvas_config(priv->canvas, priv->canvas_id_vd1_1,
priv->viu.vd1_addr1, priv->viu.vd1_stride1,
priv->viu.vd1_height1, MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR, MESON_CANVAS_ENDIAN_SWAP64);
case 1:
meson_canvas_config(priv->canvas, priv->canvas_id_vd1_0,
priv->viu.vd1_addr0, priv->viu.vd1_stride0,
priv->viu.vd1_height0, MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR, MESON_CANVAS_ENDIAN_SWAP64);
};

writel_relaxed(priv->viu.vd1_if0_gen_reg,
priv->io_base + _REG(VD1_IF0_GEN_REG));
writel_relaxed(priv->viu.vd1_if0_gen_reg,
priv->io_base + _REG(VD2_IF0_GEN_REG));
writel_relaxed(priv->viu.vd1_if0_gen_reg2,
priv->io_base + _REG(VD1_IF0_GEN_REG2));
writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
priv->io_base + _REG(VIU_VD1_FMT_CTRL));
writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
priv->io_base + _REG(VIU_VD2_FMT_CTRL));
writel_relaxed(priv->viu.viu_vd1_fmt_w,
priv->io_base + _REG(VIU_VD1_FMT_W));
writel_relaxed(priv->viu.viu_vd1_fmt_w,
priv->io_base + _REG(VIU_VD2_FMT_W));
writel_relaxed(priv->viu.vd1_if0_canvas0,
priv->io_base + _REG(VD1_IF0_CANVAS0));
writel_relaxed(priv->viu.vd1_if0_canvas0,
priv->io_base + _REG(VD1_IF0_CANVAS1));
writel_relaxed(priv->viu.vd1_if0_canvas0,
priv->io_base + _REG(VD2_IF0_CANVAS0));
writel_relaxed(priv->viu.vd1_if0_canvas0,
priv->io_base + _REG(VD2_IF0_CANVAS1));
writel_relaxed(priv->viu.vd1_if0_luma_x0,
priv->io_base + _REG(VD1_IF0_LUMA_X0));
writel_relaxed(priv->viu.vd1_if0_luma_x0,
priv->io_base + _REG(VD1_IF0_LUMA_X1));
writel_relaxed(priv->viu.vd1_if0_luma_x0,
priv->io_base + _REG(VD2_IF0_LUMA_X0));
writel_relaxed(priv->viu.vd1_if0_luma_x0,
priv->io_base + _REG(VD2_IF0_LUMA_X1));
writel_relaxed(priv->viu.vd1_if0_luma_y0,
priv->io_base + _REG(VD1_IF0_LUMA_Y0));
writel_relaxed(priv->viu.vd1_if0_luma_y0,
priv->io_base + _REG(VD1_IF0_LUMA_Y1));
writel_relaxed(priv->viu.vd1_if0_luma_y0,
priv->io_base + _REG(VD2_IF0_LUMA_Y0));
writel_relaxed(priv->viu.vd1_if0_luma_y0,
priv->io_base + _REG(VD2_IF0_LUMA_Y1));
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
priv->io_base + _REG(VD1_IF0_CHROMA_X0));
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
priv->io_base + _REG(VD1_IF0_CHROMA_X1));
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
priv->io_base + _REG(VD2_IF0_CHROMA_X0));
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
priv->io_base + _REG(VD2_IF0_CHROMA_X1));
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
priv->io_base + _REG(VD1_IF0_CHROMA_Y0));
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
priv->io_base + _REG(VD1_IF0_CHROMA_Y1));
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
priv->io_base + _REG(VD2_IF0_CHROMA_Y0));
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
priv->io_base + _REG(VD2_IF0_CHROMA_Y1));
writel_relaxed(priv->viu.vd1_if0_repeat_loop,
priv->io_base + _REG(VD1_IF0_RPT_LOOP));
writel_relaxed(priv->viu.vd1_if0_repeat_loop,
priv->io_base + _REG(VD2_IF0_RPT_LOOP));
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
priv->io_base + _REG(VD1_IF0_LUMA0_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
priv->io_base + _REG(VD2_IF0_LUMA0_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
priv->io_base + _REG(VD1_IF0_LUMA1_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
priv->io_base + _REG(VD2_IF0_LUMA1_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
priv->io_base + _REG(VD1_IF0_CHROMA0_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
priv->io_base + _REG(VD2_IF0_CHROMA0_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
priv->io_base + _REG(VD1_IF0_CHROMA1_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
priv->io_base + _REG(VD2_IF0_CHROMA1_RPT_PAT));
writel_relaxed(0, priv->io_base + _REG(VD1_IF0_LUMA_PSEL));
writel_relaxed(0, priv->io_base + _REG(VD1_IF0_CHROMA_PSEL));
writel_relaxed(0, priv->io_base + _REG(VD2_IF0_LUMA_PSEL));
writel_relaxed(0, priv->io_base + _REG(VD2_IF0_CHROMA_PSEL));
writel_relaxed(priv->viu.vd1_range_map_y,
priv->io_base + _REG(VD1_IF0_RANGE_MAP_Y));
writel_relaxed(priv->viu.vd1_range_map_cb,
priv->io_base + _REG(VD1_IF0_RANGE_MAP_CB));
writel_relaxed(priv->viu.vd1_range_map_cr,
priv->io_base + _REG(VD1_IF0_RANGE_MAP_CR));
writel_relaxed(0x78404,
priv->io_base + _REG(VPP_SC_MISC));
writel_relaxed(priv->viu.vpp_pic_in_height,
priv->io_base + _REG(VPP_PIC_IN_HEIGHT));
writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,
priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END));
writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,
priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,
priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END));
writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,
priv->io_base + _REG(VPP_BLEND_VD2_V_START_END));
writel_relaxed(priv->viu.vpp_hsc_region12_startp,
priv->io_base + _REG(VPP_HSC_REGION12_STARTP));
writel_relaxed(priv->viu.vpp_hsc_region34_startp,
priv->io_base + _REG(VPP_HSC_REGION34_STARTP));
writel_relaxed(priv->viu.vpp_hsc_region4_endp,
priv->io_base + _REG(VPP_HSC_REGION4_ENDP));
writel_relaxed(priv->viu.vpp_hsc_start_phase_step,
priv->io_base + _REG(VPP_HSC_START_PHASE_STEP));
writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,
priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE));
writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,
priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE));
writel_relaxed(priv->viu.vpp_line_in_length,
priv->io_base + _REG(VPP_LINE_IN_LENGTH));
writel_relaxed(priv->viu.vpp_preblend_h_size,
priv->io_base + _REG(VPP_PREBLEND_H_SIZE));
writel_relaxed(priv->viu.vpp_vsc_region12_startp,
priv->io_base + _REG(VPP_VSC_REGION12_STARTP));
writel_relaxed(priv->viu.vpp_vsc_region34_startp,
priv->io_base + _REG(VPP_VSC_REGION34_STARTP));
writel_relaxed(priv->viu.vpp_vsc_region4_endp,
priv->io_base + _REG(VPP_VSC_REGION4_ENDP));
writel_relaxed(priv->viu.vpp_vsc_start_phase_step,
priv->io_base + _REG(VPP_VSC_START_PHASE_STEP));
writel_relaxed(priv->viu.vpp_vsc_ini_phase,
priv->io_base + _REG(VPP_VSC_INI_PHASE));
writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,
priv->io_base + _REG(VPP_VSC_PHASE_CTRL));
writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,
priv->io_base + _REG(VPP_HSC_PHASE_CTRL));
writel_relaxed(0x00000042,
priv->io_base + _REG(VPP_SCALE_COEF_IDX));

/* Enable VD1 */
writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | VPP_COLOR_MNG_ENABLE,
VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | VPP_COLOR_MNG_ENABLE,
priv->io_base + _REG(VPP_MISC));

priv->viu.vd1_commit = false;
}

drm_crtc_handle_vblank(priv->crtc);

spin_lock_irqsave(&priv->drm->event_lock, flags);
Expand Down
14 changes: 14 additions & 0 deletions drivers/gpu/drm/meson/meson_drv.c
View file
Expand Up @@ -41,6 +41,7 @@

#include "meson_drv.h"
#include "meson_plane.h"
#include "meson_overlay.h"
#include "meson_crtc.h"
#include "meson_venc_cvbs.h"

Expand Down Expand Up @@ -222,6 +223,15 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
}

ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
if (ret)
goto free_drm;
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
if (ret)
goto free_drm;
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
if (ret)
goto free_drm;
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
if (ret)
goto free_drm;

Expand Down Expand Up @@ -261,6 +271,10 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
if (ret)
goto free_drm;

ret = meson_overlay_create(priv);
if (ret)
goto free_drm;

ret = meson_crtc_create(priv);
if (ret)
goto free_drm;
Expand Down
52 changes: 52 additions & 0 deletions drivers/gpu/drm/meson/meson_drv.h
View file
Expand Up @@ -33,11 +33,15 @@ struct meson_drm {

struct meson_canvas *canvas;
u8 canvas_id_osd1;
u8 canvas_id_vd1_0;
u8 canvas_id_vd1_1;
u8 canvas_id_vd1_2;

struct drm_device *drm;
struct drm_crtc *crtc;
struct drm_fbdev_cma *fbdev;
struct drm_plane *primary_plane;
struct drm_plane *overlay_plane;

/* Components Data */
struct {
Expand All @@ -49,6 +53,54 @@ struct meson_drm {
uint32_t osd1_addr;
uint32_t osd1_stride;
uint32_t osd1_height;

bool vd1_enabled;
bool vd1_commit;
unsigned int vd1_planes;
uint32_t vd1_if0_gen_reg;
uint32_t vd1_if0_luma_x0;
uint32_t vd1_if0_luma_y0;
uint32_t vd1_if0_chroma_x0;
uint32_t vd1_if0_chroma_y0;
uint32_t vd1_if0_repeat_loop;
uint32_t vd1_if0_luma0_rpt_pat;
uint32_t vd1_if0_chroma0_rpt_pat;
uint32_t vd1_range_map_y;
uint32_t vd1_range_map_cb;
uint32_t vd1_range_map_cr;
uint32_t viu_vd1_fmt_w;
uint32_t vd1_if0_canvas0;
uint32_t vd1_if0_gen_reg2;
uint32_t viu_vd1_fmt_ctrl;
uint32_t vd1_addr0;
uint32_t vd1_addr1;
uint32_t vd1_addr2;
uint32_t vd1_stride0;
uint32_t vd1_stride1;
uint32_t vd1_stride2;
uint32_t vd1_height0;
uint32_t vd1_height1;
uint32_t vd1_height2;
uint32_t vpp_pic_in_height;
uint32_t vpp_postblend_vd1_h_start_end;
uint32_t vpp_postblend_vd1_v_start_end;
uint32_t vpp_hsc_region12_startp;
uint32_t vpp_hsc_region34_startp;
uint32_t vpp_hsc_region4_endp;
uint32_t vpp_hsc_start_phase_step;
uint32_t vpp_hsc_region1_phase_slope;
uint32_t vpp_hsc_region3_phase_slope;
uint32_t vpp_line_in_length;
uint32_t vpp_preblend_h_size;
uint32_t vpp_vsc_region12_startp;
uint32_t vpp_vsc_region34_startp;
uint32_t vpp_vsc_region4_endp;
uint32_t vpp_vsc_start_phase_step;
uint32_t vpp_vsc_ini_phase;
uint32_t vpp_vsc_phase_ctrl;
uint32_t vpp_hsc_phase_ctrl;
uint32_t vpp_blend_vd2_h_start_end;
uint32_t vpp_blend_vd2_v_start_end;
} viu;

struct {
Expand Down

0 comments on commit a428200

Please sign in to comment.