drm/meson: init g12a osd2 yuv2rgb instead of osd1

Following vendor change, to avoid:
> green line displayed when osd alpha 0xff/0x00 continuos
replace yuv2rgb of osd1 for osd2 for G12A & compatible SoCs.

Fixes: 7288839 ("drm/meson: Add G12A Support for VIU setup")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

drivers/gpu/drm/meson/meson_viu.c

@@ -78,32 +78,32 @@ static int eotf_bypass_coeff[EOTF_COEFF_SIZE] = {
 	EOTF_COEFF_RIGHTSHIFT /* right shift */
 };
 
-static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv,
+static void meson_viu_set_g12a_osd2_matrix(struct meson_drm *priv,
 					   int *m, bool csc_on)
 {
-	/* VPP WRAP OSD1 matrix */
+	/* VPP WRAP OSD2 matrix */
 	writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1));
 	writel(m[2] & 0xfff,
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2));
 	writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF00_01));
 	writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF02_10));
 	writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF11_12));
 	writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF20_21));
 	writel((m[11] & 0x1fff) << 16,
-		priv->io_base +	_REG(VPP_WRAP_OSD1_MATRIX_COEF22));
+		priv->io_base +	_REG(VPP_WRAP_OSD2_MATRIX_COEF22));
 
 	writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_OFFSET0_1));
 	writel(m[20] & 0xfff,
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_OFFSET2));
 
 	writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
-		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
+		priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_EN_CTRL));
 }
 
 static void meson_viu_set_osd_matrix(struct meson_drm *priv,
@@ -360,7 +360,7 @@ void meson_viu_init(struct meson_drm *priv)
 	    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 		meson_viu_load_matrix(priv);
 	else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
-		meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
+		meson_viu_set_g12a_osd2_matrix(priv, RGB709_to_YUV709l_coeff,
 					       true);
 
 	/* Initialize OSD1 fifo control register */