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  • vdf-fpga

    Implementation of an RSA VDF evaluator targeting FPGAs.

    SystemVerilog 6 15 0 0 Updated Aug 11, 2019
  • lcs35

    Code related to solving the LCS35 timelock puzzle.

    SystemVerilog Apache-2.0 0 2 0 0 Updated May 18, 2019
  • primitives

    Low level arithmetic primitives in RTL

    SystemVerilog Apache-2.0 0 4 0 0 Updated May 9, 2019

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