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1. Project_Lift Project_Lift Public

   Simulating the working of an elevator using verilog hld coding and running it on an FPGA

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2. async_fifo async_fifo Public

   Simulation of an asynchronous fifo/buffer used to transfer data between different clock domains using verilog

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3. Communication-and-Encryption-Between-Different-Networks Communication-and-Encryption-Between-Different-Networks Public

   Forked from DhruvSrikanth/Communication-and-Encryption-Between-Different-Networks

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4. Acute-Infarct-DL Acute-Infarct-DL Public

   Forked from Maithilishetty/Acute-Infarct-DL

   Acute Infarct Location Classification using CNN.

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5. mergesort_openmp mergesort_openmp Public

   Implementation of parallel mergesort using OpenMP dierectives

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6. MIPS_Processors MIPS_Processors Public

   Verilog implementation of the MIPS single cycle, multi cycle and pipeline processor architectures

   Verilog