add xor,xnor and tests #1206

ranjithkumar007 · 2017-02-02T11:09:00Z

No description provided.

isuruf · 2017-02-04T05:00:32Z

symengine/logic.cpp

+        if (eq(*a, *boolTrue)) {
+            cnttrue++;
+        }
+    }


This function only checks for trues and false. logical_xor(x, y) would give false.

isuruf

Please don't do git add .. There's a binary file commited here, symengine/stap7FQc

isuruf · 2017-02-09T09:48:43Z

symengine/logic.cpp

@@ -352,6 +404,43 @@ RCP<const Boolean> logical_not(const RCP<const Boolean> &s)
    }
 }

+RCP<const Boolean> logical_xor(const set_boolean &s)


If you use a set here, how would you pass x, x

need to change this....Same problem is with all other gates!

Or and And is fine.

symbols can be used as parameters if set_boolean is replaced by set_basic.

From x I meant the same boolean. for example, y < 0, y < 0 where y is a symbol.

ranjithkumar007 · 2017-02-11T14:23:50Z

@isuruf ,any idea why this job is failing?
Based on exec time 0.65s , i feel that the cause might be an infinite recursion but unable to figure out exactly...!

isuruf · 2017-02-11T14:27:08Z

symengine/logic.cpp

+    for (auto &a : s) {
+        if (is_a<BooleanAtom>(*a)) {
+            auto val = down_cast<const BooleanAtom &>(*a).get_val();
+            if (val == false) {


Why is false ignored?

because Xor(args,false) = Xor(args)

isuruf · 2017-02-11T14:30:08Z

symengine/logic.cpp

+            if (is_a<BooleanAtom>(*a)) {
+                SYMENGINE_ASSERT(a == boolTrue)
+                args.erase(a);
+                return logical_xnor(get_vec_from_set(args));


For performance reasons, these type of recursion should be avoided.

yes.. i would convert it to iterative way..

isuruf · 2017-02-11T16:23:50Z

symengine/logic.cpp

        for (auto &a : args) {
            if (is_a<BooleanAtom>(*a)) {
                SYMENGINE_ASSERT(a == boolTrue)
                args.erase(a);
-                return logical_xnor(get_vec_from_set(args));
+                cantsimplify = false;
+                nots++;
            } else if (args.find(logical_not(a)) != args.end()) {


This can be checked in Line 447 and don't need to do this here.

isuruf · 2017-02-11T16:24:15Z

symengine/logic.cpp

        for (auto &a : args) {
            if (is_a<BooleanAtom>(*a)) {
                SYMENGINE_ASSERT(a == boolTrue)
                args.erase(a);
-                return logical_xnor(get_vec_from_set(args));
+                cantsimplify = false;
+                nots++;


You can do this in the if condition in line 429

isuruf · 2017-02-11T16:24:47Z

symengine/logic.cpp

-    } else if (args.size() == 1) {
-        return *args.begin();
-    } else {
+    while (args.size() > 1 and not cantsimplify) {


why is this run multiple times?

isuruf · 2017-02-11T16:25:14Z

symengine/logic.cpp

-        return *args.begin();
-    } else {
+    while (args.size() > 1 and not cantsimplify) {
+        cantsimplify = true;
        for (auto &a : args) {
            if (is_a<BooleanAtom>(*a)) {
                SYMENGINE_ASSERT(a == boolTrue)
                args.erase(a);


You are erasing from the vector while iterating it. Segfaults can happen if you do that.

ranjithkumar007 · 2017-02-20T13:16:30Z

ping @isuruf

isuruf · 2017-02-20T13:18:45Z

symengine/logic.cpp

+                    args.erase(aa);
+                } else {
+                    args.insert(aa);
+                    if (args.find(logical_not(aa)) != args.end()) {


Store args.find(logical_not(aa)) so that you don't have to call this below as wel.

isuruf · 2017-02-20T13:19:04Z

symengine/logic.cpp

+                if (args.find(aa) != args.end()) {
+                    args.erase(aa);
+                } else {
+                    args.insert(aa);


Insert this only if the following if command is not true

isuruf · 2017-02-20T13:19:46Z

symengine/logic.cpp

+            args.erase(a);
+        } else {
+            args.insert(a);
+            if (args.find(logical_not(a)) != args.end()) {


isuruf · 2017-02-20T13:19:51Z

symengine/logic.cpp

+        if (args.find(a) != args.end()) {
+            args.erase(a);
+        } else {
+            args.insert(a);


ranjithkumar007 · 2017-02-28T17:15:17Z

ping @isuruf

add xor,xnor and tests

ranjithkumar007 force-pushed the xor branch from a296b17 to 18ed390 Compare February 2, 2017 15:05

isuruf reviewed Feb 4, 2017

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isuruf requested changes Feb 4, 2017

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ranjithkumar007 force-pushed the xor branch 2 times, most recently from c04f601 to 4b19a41 Compare February 5, 2017 10:09

add xor,xnor and tests

4dbfb00

ranjithkumar007 force-pushed the xor branch from 4b19a41 to 4dbfb00 Compare February 5, 2017 10:13

isuruf reviewed Feb 9, 2017

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use vec_boolean

6d426fe

ranjithkumar007 force-pushed the xor branch from ccbf8ab to 6d426fe Compare February 10, 2017 13:36

isuruf requested changes Feb 11, 2017

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ranjithkumar007 force-pushed the xor branch 3 times, most recently from 009b198 to a431ed8 Compare February 12, 2017 11:00

isuruf reviewed Feb 20, 2017

View reviewed changes

improve implementation and add tests

4f80d46

ranjithkumar007 force-pushed the xor branch from a431ed8 to 4f80d46 Compare February 20, 2017 16:25

isuruf merged commit ed643cb into symengine:master Feb 28, 2017

ranjithkumar007 deleted the xor branch February 28, 2017 17:54

isuruf added a commit to isuruf/symengine that referenced this pull request Aug 4, 2018

Merge pull request symengine#1206 from ranjithkumar007/xor

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add xor,xnor and tests

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add xor,xnor and tests #1206

add xor,xnor and tests #1206

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ranjithkumar007 commented Feb 28, 2017

add xor,xnor and tests #1206

add xor,xnor and tests #1206

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ranjithkumar007 commented Feb 2, 2017

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ranjithkumar007 commented Feb 11, 2017

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ranjithkumar007 commented Feb 20, 2017

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ranjithkumar007 commented Feb 28, 2017