Bad fmax after switch to Chisel 3

[schoeberl]

Chisel 3 does not create a Verilog case statement, but priority MUXs (see chipsalliance/chisel#983). This hurts fmax (also for Chisel switch statements, e.g., an ALU lookup in Leros). A workaround is to generate an inline Verilog table (case).

[schoeberl]

Fixed by #108