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Add force-amo feature (portable_atomic_force_amo cfg) #124

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Oct 15, 2023
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@taiki-e taiki-e commented Oct 10, 2023

On RISC-V (without A-extension) with the force-amo feature, this uses AMO instructions for RMWs that have corresponding AMO instructions even if A-extension is disabled. For other RMWs, this disables interrupts as usual.

Some operations don't require disabling interrupts (loads and stores on targets except for AVR, but additionally on MSP430 {8,16}-bit add,sub,and,or,xor,not, on RISC-V with the force-amo feature 32-bit(RV32)/{32,64}-bit(RV64) swap,fetch_{add,sub,and,or,xor,not,max,min},add,sub,and,or,xor,not and {8,16}-bit fetch_{and,or,xor,not},and,or,xor,not). However, when the critical-section feature is enabled, critical sections are taken for all atomic operations.

Closes #123

This feature requires Rust 1.72+ because .option arch requires it. (rust-lang/llvm-project#147)
Currently, enabling this on older compilers will result in an error, but it might be better to fallback to implementation disabling interrupts.

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taiki-e commented Oct 15, 2023

fallback to implementation disabling interrupts.

I won't implement it for now, but if anyone actually needs this, I'll consider implementing it.

@taiki-e taiki-e merged commit 9ee156e into main Oct 15, 2023
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@taiki-e taiki-e deleted the riscv-amo branch October 15, 2023 02:47
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Is there a mechanism to emulate only CAS operations?
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