[micropython#4701] Correct DAC clock speed comments for SAMD21 and SA…

…MD51
tannewt · Oct 5, 2021 · 881724b · 881724b
1 parent e8f21f0
commit 881724b
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/ports/atmel-samd/common-hal/analogio/AnalogOut.c b/ports/atmel-samd/common-hal/analogio/AnalogOut.c
@@ -85,8 +85,8 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self,
     _pm_enable_bus_clock(PM_BUS_APBC, DAC);
     #endif
 
-    // SAMD21: This clock should be <= 12 MHz, per datasheet section 47.6.3.
-    // SAMD51: This clock should be <= 350kHz, per datasheet table 37-6.
+    // SAMD21: This clock should be <= 350 kHz, per datasheet table 36-7.
+    // SAMD51: This clock should be <= 12 MHz, per datasheet section 47.6.3.
     _gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC);
 
     // Don't double init the DAC on the SAMD51 when both outputs are in use. We use the free state