Update google_riscv-dv to b4bd0c6

Update code from upstream repository https://github.com/google/riscv-
dv to revision b4bd0c6cff0456111be966a11c1bd0aeec2d96e4

* Merge pull request lowRISC#24 from google/dev (taoliug)
* Add option to skip reading scratch register (Tao Liu)

vendor/google_riscv-dv.lock.hjson

@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/google/riscv-dv
-    rev: be14080425cc3b9a5b33c6c29962893c890c62ee
+    rev: b4bd0c6cff0456111be966a11c1bd0aeec2d96e4
   }
 }

vendor/google_riscv-dv/src/riscv_asm_program_gen.sv

@@ -245,6 +245,11 @@ class riscv_asm_program_gen extends uvm_object;
 
   virtual function void gen_program_header();
     // ------------- IBEX modification start --------------------
+    // Override the cfg value, below field is not supported by ibex
+    cfg.mstatus_mprv = 0;
+    cfg.mstatus_mxr  = 0;
+    cfg.mstatus_sum  = 0;
+    cfg.mstatus_tvm  = 0;
     // The ibex core load the program from 0x80
     // Some address is reserved for hardware interrupt handling, need to decide if we need to copy
     // the init program from crt0.S later.
@@ -255,7 +260,19 @@ class riscv_asm_program_gen extends uvm_object;
     instr_stream.push_back("j _start");
     // Align the start section to 0x80
     instr_stream.push_back(".align 7");
-    instr_stream.push_back("_start:");
+    instr_stream.push_back("_start: j _reset_entry");
+    // ibex reserves 0x84-0x8C for trap handling, redirect everything mtvec_handler
+    // 0x84 illegal instruction
+    instr_stream.push_back(".align 2");
+    instr_stream.push_back("j mtvec_handler");
+    // 0x88 ECALL instruction handler
+    instr_stream.push_back(".align 2");
+    instr_stream.push_back("j mtvec_handler");
+    // 0x8C LSU error
+    instr_stream.push_back(".align 2");
+    instr_stream.push_back("j mtvec_handler");
+    // Starting point of the reset entry
+    instr_stream.push_back("_reset_entry:");
     // ------------- IBEX modification end --------------------
   endfunction
 

vendor/google_riscv-dv/src/riscv_core_setting.sv

@@ -82,43 +82,15 @@ int kernel_program_instr_cnt = 400;
 
 // Implemented previlieged CSR list
 privileged_reg_t implemented_csr[$] = {
-    // User mode CSR
-    USTATUS,    // User status
-    UIE,        // User interrupt-enable register
-    UTVEC,      // User trap-handler base address
-    USCRATCH,   // Scratch register for user trap handlers
-    UEPC,       // User exception program counter
-    UCAUSE,     // User trap cause
-    UTVAL,      // User bad address or instruction
-    UIP,        // User interrupt pending
-    // Supervisor mode CSR
-    SSTATUS,    // Supervisor status
-    SEDELEG,    // Supervisor exception delegation register
-    SIDELEG,    // Supervisor interrupt delegation register
-    SIE,        // Supervisor interrupt-enable register
-    STVEC,      // Supervisor trap-handler base address
-    SCOUNTEREN, // Supervisor counter enable
-    SSCRATCH,   // Scratch register for supervisor trap handlers
-    SEPC,       // Supervisor exception program counter
-    SCAUSE,     // Supervisor trap cause
-    STVAL,      // Supervisor bad address or instruction
-    SIP,        // Supervisor interrupt pending
-    SATP,       // Supervisor address translation and protection
     // Machine mode mode CSR
     MVENDORID,  // Vendor ID
     MARCHID,    // Architecture ID
-    MIMPID,     // Implementation ID
     MHARTID,    // Hardware thread ID
     MSTATUS,    // Machine status
     MISA,       // ISA and extensions
-    MEDELEG,    // Machine exception delegation register
-    MIDELEG,    // Machine interrupt delegation register
-    MIE,        // Machine interrupt-enable register
     MTVEC,      // Machine trap-handler base address
-    MCOUNTEREN, // Machine counter enable
-    MSCRATCH,   // Scratch register for machine trap handlers
     MEPC,       // Machine exception program counter
     MCAUSE,     // Machine trap cause
-    MTVAL,      // Machine bad address or instruction
-    MIP         // Machine interrupt pending
+    MTVAL       // Machine bad address or instruction
+    // TODO: Add performance CSRs and debug mode CSR
 };

vendor/google_riscv-dv/src/riscv_instr_pkg.sv

@@ -682,11 +682,13 @@ package riscv_instr_pkg;
                                                    bit mprv,
                                                    ref string instr[$]);
     string store_instr = (XLEN == 32) ? "sw" : "sd";
-    // Use kernal stack for handling exceptions
-    // Save the user mode stack pointer to the scratch register
-    instr.push_back($sformatf("csrrw sp, 0x%0x, sp", scratch));
-    // Move TP to SP
-    instr.push_back("add sp, tp, zero");
+    if (scratch inside {implemented_csr}) begin
+      // Use kernal stack for handling exceptions
+      // Save the user mode stack pointer to the scratch register
+      instr.push_back($sformatf("csrrw sp, 0x%0x, sp", scratch));
+      // Move TP to SP
+      instr.push_back("add sp, tp, zero");
+    end
     // If MPRV is set and MPP is S/U mode, it means the address translation and memory protection
     // for load/store instruction is the same as the mode indicated by MPP. In this case, we
     // need to use the virtual address to access the kernel stack.
@@ -724,10 +726,12 @@ package riscv_instr_pkg;
     end
     // Restore kernel stack pointer
     instr.push_back($sformatf("addi sp, sp, %0d", 32 * (XLEN/8)));
-    // Move SP to TP
-    instr.push_back("add tp, sp, zero");
-    // Restore user mode stack pointer
-    instr.push_back($sformatf("csrrw sp, 0x%0x, sp", scratch));
+    if (scratch inside {implemented_csr}) begin
+      // Move SP to TP
+      instr.push_back("add tp, sp, zero");
+      // Restore user mode stack pointer
+      instr.push_back($sformatf("csrrw sp, 0x%0x, sp", scratch));
+    end
   endfunction
 
   `include "riscv_instr_gen_config.sv"

vendor/google_riscv-dv/testlist

@@ -24,6 +24,6 @@ riscv_mmu_stress_test           : 10
 riscv_page_table_exception_test : 0
 riscv_no_fence_test             : 10
 riscv_sfence_exception_test     : 0
-riscv_illegal_instr_test        : 10
+riscv_illegal_instr_test        : 1
 riscv_hint_instr_test           : 10
 //------------------------------------------------