formatted astyle -A10 -s2

teachop · Mar 25, 2014 · d536db8 · d536db8
1 parent f0d1880
commit d536db8
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Showing 4 changed files with 60 additions and 45 deletions.
diff --git a/FlexCAN.cpp b/FlexCAN.cpp
@@ -40,16 +40,16 @@ FlexCAN::FlexCAN(uint32_t baud)
   // segment timings from freescale loopback test
   if ( 250000 == baud ) {
     FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(1)
-                    | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(15));
+                      | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(15));
   } else if ( 500000 == baud ) {
     FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(1)
-                    | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(7));
+                      | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(7));
   } else if ( 1000000 == baud ) {
     FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(3) | FLEXCAN_CTRL_RJW(0)
-                    | FLEXCAN_CTRL_PSEG1(0) | FLEXCAN_CTRL_PSEG2(1) | FLEXCAN_CTRL_PRESDIV(5));
+                      | FLEXCAN_CTRL_PSEG1(0) | FLEXCAN_CTRL_PSEG2(1) | FLEXCAN_CTRL_PRESDIV(5));
   } else { // 125000
     FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(2)
-                    | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(31));
+                      | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(31));
   }
 
   // Default mask is allow everything
@@ -75,17 +75,18 @@ void FlexCAN::begin(const CAN_filter_t &mask)
   FLEXCAN0_RXMGMASK = 0;
 
   //enable reception of all messages that fit the mask
-  if (mask.ext)
+  if (mask.ext) {
     FLEXCAN0_RXFGMASK = ((mask.rtr?1:0) << 31) | ((mask.ext?1:0) << 30) | ((mask.id & FLEXCAN_MB_ID_EXT_MASK) << 1);
-  else
+  } else {
     FLEXCAN0_RXFGMASK = ((mask.rtr?1:0) << 31) | ((mask.ext?1:0) << 30) | (FLEXCAN_MB_ID_IDSTD(mask.id) << 1);
+  }
 
   // start the CAN
   FLEXCAN0_MCR &= ~(FLEXCAN_MCR_HALT);
   // wait till exit of freeze mode
   while(FLEXCAN0_MCR & FLEXCAN_MCR_FRZ_ACK);
 
-  // wait till ready 
+  // wait till ready
   while(FLEXCAN0_MCR & FLEXCAN_MCR_NOT_RDY);
 
   //set tx buffers to inactive
@@ -99,10 +100,11 @@ void FlexCAN::begin(const CAN_filter_t &mask)
 void FlexCAN::setFilter(const CAN_filter_t &filter, uint8_t n)
 {
   if ( 8 > n ) {
-    if (filter.ext)
+    if (filter.ext) {
       FLEXCAN0_IDFLT_TAB(n) = ((filter.rtr?1:0) << 31) | ((filter.ext?1:0) << 30) | ((filter.id & FLEXCAN_MB_ID_EXT_MASK) << 1);
-    else
+    } else {
       FLEXCAN0_IDFLT_TAB(n) = ((filter.rtr?1:0) << 31) | ((filter.ext?1:0) << 30) | (FLEXCAN_MB_ID_IDSTD(filter.id) << 1);
+    }
   }
 }
 
@@ -130,7 +132,7 @@ int FlexCAN::read(CAN_message_t &msg)
     }
     yield();
   }
-  
+
   // get identifier and dlc
   msg.len = FLEXCAN_get_length(FLEXCAN0_MBn_CS(rxb));
   msg.ext = (FLEXCAN0_MBn_CS(rxb) & FLEXCAN_MB_CS_IDE)? 1:0;
@@ -141,15 +143,21 @@ int FlexCAN::read(CAN_message_t &msg)
 
   // copy out message
   uint32_t dataIn = FLEXCAN0_MBn_WORD0(rxb);
-  msg.buf[3] = dataIn; dataIn >>=8;
-  msg.buf[2] = dataIn; dataIn >>=8;
-  msg.buf[1] = dataIn; dataIn >>=8;
+  msg.buf[3] = dataIn;
+  dataIn >>=8;
+  msg.buf[2] = dataIn;
+  dataIn >>=8;
+  msg.buf[1] = dataIn;
+  dataIn >>=8;
   msg.buf[0] = dataIn;
   if ( 4 < msg.len ) {
     dataIn = FLEXCAN0_MBn_WORD1(rxb);
-    msg.buf[7] = dataIn; dataIn >>=8;
-    msg.buf[6] = dataIn; dataIn >>=8;
-    msg.buf[5] = dataIn; dataIn >>=8;
+    msg.buf[7] = dataIn;
+    dataIn >>=8;
+    msg.buf[6] = dataIn;
+    dataIn >>=8;
+    msg.buf[5] = dataIn;
+    dataIn >>=8;
     msg.buf[4] = dataIn;
   }
   for( int loop=msg.len; loop<8; ++loop ) {
@@ -170,7 +178,7 @@ int FlexCAN::write(const CAN_message_t &msg)
   if ( msg.timeout ) {
     startMillis = millis();
   }
-  
+
   // find an available buffer
   int buffer = -1;
   for ( int index = txb; ; ) {
@@ -202,10 +210,10 @@ int FlexCAN::write(const CAN_message_t &msg)
   FLEXCAN0_MBn_WORD1(buffer) = (msg.buf[4]<<24)|(msg.buf[5]<<16)|(msg.buf[6]<<8)|msg.buf[7];
   if(msg.ext) {
     FLEXCAN0_MBn_CS(buffer) = FLEXCAN_MB_CS_CODE(FLEXCAN_MB_CODE_TX_ONCE)
-                      | FLEXCAN_MB_CS_LENGTH(msg.len) | FLEXCAN_MB_CS_SRR | FLEXCAN_MB_CS_IDE;
+                              | FLEXCAN_MB_CS_LENGTH(msg.len) | FLEXCAN_MB_CS_SRR | FLEXCAN_MB_CS_IDE;
   } else {
     FLEXCAN0_MBn_CS(buffer) = FLEXCAN_MB_CS_CODE(FLEXCAN_MB_CODE_TX_ONCE)
-                      | FLEXCAN_MB_CS_LENGTH(msg.len);
+                              | FLEXCAN_MB_CS_LENGTH(msg.len);
   }
 
   return 1;

diff --git a/FlexCAN.h b/FlexCAN.h
@@ -4,31 +4,33 @@
 //
 #include <Arduino.h>
 
-typedef struct CAN_message_t
-{
+typedef struct CAN_message_t {
   uint32_t id; // can identifier
   uint8_t ext; // identifier is extended
   uint8_t len; // length of data
   uint16_t timeout; // milliseconds, zero will disable waiting
   uint8_t buf[8];
 } CAN_message_t;
 
-typedef struct CAN_filter_t
-{
+typedef struct CAN_filter_t {
   uint8_t rtr;
   uint8_t ext;
   uint32_t id;
 } CAN_filter_t;
 
 // -------------------------------------------------------------
-class FlexCAN {
+class FlexCAN
+{
 private:
   struct CAN_filter_t defaultMask;
 
 public:
   FlexCAN(uint32_t baud = 125000);
   void begin(const CAN_filter_t &mask);
-  inline void begin() { begin(defaultMask);}
+  inline void begin()
+  {
+    begin(defaultMask);
+  }
   void setFilter(const CAN_filter_t &filter, uint8_t n);
   void end(void);
   int available(void);

diff --git a/examples/CANtest/CANtest.ino b/examples/CANtest/CANtest.ino
@@ -23,7 +23,8 @@ unsigned int txTimer,rxTimer;
 
 
 // -------------------------------------------------------------
-static void hexDump(uint8_t dumpLen, uint8_t *bytePtr) {
+static void hexDump(uint8_t dumpLen, uint8_t *bytePtr)
+{
   uint8_t working;
   while( dumpLen-- ) {
     working = *bytePtr++;
@@ -44,7 +45,7 @@ void setup(void)
 
   delay(1000);
   Serial.println(F("Hello Teensy 3.1 CAN Test."));
-  
+
   sysTimer.reset();
 }
 
@@ -54,10 +55,14 @@ void loop(void)
 {
   // service software timers based on Metro tick
   if ( sysTimer.check() ) {
-    if ( txTimer ) --txTimer;
-    if ( rxTimer ) --rxTimer;
+    if ( txTimer ) {
+      --txTimer;
+    }
+    if ( rxTimer ) {
+      --rxTimer;
+    }
   }
-  
+
   // if not time-delayed, read CAN messages and print 1st byte
   if ( !rxTimer ) {
     while ( CANbus.read(rxmsg) ) {

diff --git a/kinetis_flexcan.h b/kinetis_flexcan.h
@@ -80,7 +80,7 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN0_DBG2                  (*(vuint32_t*)(FLEXCAN0_BASE+0x5C))
 
 #define FLEXCAN0_IMEUR                 FLEXCAN0_FUREQ
-#define FLEXCAN0_LRFR                  FLEXCAN0_FUACK					
+#define FLEXCAN0_LRFR                  FLEXCAN0_FUACK
 
 
 /* Message Buffers */
@@ -89,7 +89,7 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN0_MB0_WORD0             (*(vuint32_t*)(FLEXCAN0_BASE+0x88))
 #define FLEXCAN0_MB0_WORD1             (*(vuint32_t*)(FLEXCAN0_BASE+0x8C))
 
-#define FLEXCAN0_MBn_CS(n)			(*(vuint32_t*)(FLEXCAN0_BASE+0x80+n*0x10))	
+#define FLEXCAN0_MBn_CS(n)			(*(vuint32_t*)(FLEXCAN0_BASE+0x80+n*0x10))
 #define FLEXCAN0_MBn_ID(n)			(*(vuint32_t*)(FLEXCAN0_BASE+0x84+n*0x10))
 #define FLEXCAN0_MBn_WORD0(n)		(*(vuint32_t*)(FLEXCAN0_BASE+0x88+n*0x10))
 #define FLEXCAN0_MBn_WORD1(n)		(*(vuint32_t*)(FLEXCAN0_BASE+0x8C+n*0x10))
@@ -158,15 +158,15 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN1_DBG2                  (*(vuint32_t*)(FLEXCAN1_BASE+0x5C))
 
 #define FLEXCAN1_IMEUR                 FLEXCAN1_FUREQ
-#define FLEXCAN1_LRFR                  FLEXCAN1_FUACK					
+#define FLEXCAN1_LRFR                  FLEXCAN1_FUACK
 
 /* Message Buffers */
 #define FLEXCAN1_MB0_CS                (*(vuint32_t*)(FLEXCAN1_BASE+0x80))
 #define FLEXCAN1_MB0_ID                (*(vuint32_t*)(FLEXCAN1_BASE+0x84))
 #define FLEXCAN1_MB0_WORD0             (*(vuint32_t*)(FLEXCAN1_BASE+0x88))
 #define FLEXCAN1_MB0_WORD1             (*(vuint32_t*)(FLEXCAN1_BASE+0x8C))
 
-#define FLEXCAN1_MBn_CS(n)		        (*(vuint32_t*)(FLEXCAN1_BASE+0x80+n*0x10))	
+#define FLEXCAN1_MBn_CS(n)		        (*(vuint32_t*)(FLEXCAN1_BASE+0x80+n*0x10))
 #define FLEXCAN1_MBn_ID(n)				(*(vuint32_t*)(FLEXCAN1_BASE+0x84+n*0x10))
 #define FLEXCAN1_MBn_WORD0(n)			(*(vuint32_t*)(FLEXCAN1_BASE+0x88+n*0x10))
 #define FLEXCAN1_MBn_WORD1(n)			(*(vuint32_t*)(FLEXCAN1_BASE+0x8C+n*0x10))
@@ -181,7 +181,7 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN1_IDFLT_TAB(n)		(*(vuint32_t*)(FLEXCAN1_BASE+0xE0+(n<<2)))
 
 /* Memory Error Control Register */
-#define FLEXCAN1_MECR					*(vuint32_t*)(FLEXCAN1_BASE+0x7B70))	
+#define FLEXCAN1_MECR					*(vuint32_t*)(FLEXCAN1_BASE+0x7B70))
 
 /* Error Injection Address Register */
 #define FLEXCAN1_ERRIAR					*(vuint32_t*)(FLEXCAN1_BASE+0x3B74))
@@ -410,7 +410,7 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN_ESR2_LOSTRLF			(0x00000004)
 #define FLEXCAN_ESR2_LOSTRMF			(0x00000002)
 #define FLEXCAN_ESR2_IMEUF				(0x00000001)
-#define FLEXCAN_get_LTM(esr2_value)	(((esr2_value) & (FLEXCAN_ESR2_LTM))>>(FLEXCAN_ESR2_LTM_BIT_NO))		
+#define FLEXCAN_get_LTM(esr2_value)	(((esr2_value) & (FLEXCAN_ESR2_LTM))>>(FLEXCAN_ESR2_LTM_BIT_NO))
 
 /* Bit definitions and macros for FLEXCAN_IMASK1 */
 #define FLEXCAN_IMASK1_BUF0M           (0x00000001)
@@ -1086,7 +1086,7 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN_IMEUR_IMEUP_BIT_NO	(0)
 #define FLEXCAN_IMEUR_IMEUREQ_MASK	(0x00000100)
 #define FLEXCAN_IMEUR_IMEUACK_MASK	(0x00000200)
-#define FLEXCAN_Set_IMEUP(imeur,imeup)	imeur = (imeur & ~(FLEXCAN_IMEUR_IMEUP_MASK)) | (imeup & FLEXCAN_IMEUR_IMEUP_MASK)  
+#define FLEXCAN_Set_IMEUP(imeur,imeup)	imeur = (imeur & ~(FLEXCAN_IMEUR_IMEUP_MASK)) | (imeup & FLEXCAN_IMEUR_IMEUP_MASK)
 #define FLEXCAN_Get_IMEUP(imeur)	(imeur & FLEXCAN_IMEUR_IMEUP_MASK)
 
 /* Bit definition for Lost Rx Frames Register (LRFR)
@@ -1099,7 +1099,7 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN_LRFR_LOSTRMP_BIT_NO		(0)
 #define FLEXCAN_Get_LostMBLocked(lrfr)	((lrfr & FLEXCAN_LRFR_LOSTRLP_MASK)>>(FLEXCAN_LRFR_LOSTRLP_BIT_NO))
 #define FLEXCAN_Get_LostMBUpdated(lrfr)	((lrfr & FLEXCAN_LRFR_LOSTRMP_MASK))
- 
+
 /* Bit definition for Memory Error Control Register */
 #define FLEXCAN_MECR_NCEFAFRZ_MASK	(0x00000080)
 #define FLEXCAN_MECR_RERRDIS_MASK	(0x00000100)
@@ -1110,24 +1110,24 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN_MECR_FANCEI_MSK_MAKS	(0x00040000)
 #define FLEXCAN_MECR_HANCEI_MSK_MAKS	(0x00080000)
 #define FLEXCAN_MECR_ECRWRDIS_MSK_MAKS	(0x80000000)
- 
+
 /* Bit definition for Error Report Address Register (RERRAR) */
 #define FLEXCAN_RERRAR_NCE_MASK		(0x01000000)
 #define FLEXCAN_RERRAR_SAID_MASK	(0x00070000)
-#define FLEXCAN_ERRADDR_MASK		(0x00003FFF) 
+#define FLEXCAN_ERRADDR_MASK		(0x00003FFF)
 
 /* Bit definition for Error Report Syndrome Register (RERRSYNR) */
 #define FLEXCAN_RERRSYNR_BE3_MASK	(0x80000000)
 #define FLEXCAN_RERRSYNR_SYND3_MASK	(0x1F000000)
 #define FLEXCAN_RERRSYNR_SYND3_BIT_NO	(24)
-#define FLEXCAN_RERRSYNR_BE2_MASK	(0x00800000) 
-#define FLEXCAN_RERRSYNR_SYND2_MASK	(0x001F0000) 
+#define FLEXCAN_RERRSYNR_BE2_MASK	(0x00800000)
+#define FLEXCAN_RERRSYNR_SYND2_MASK	(0x001F0000)
 #define FLEXCAN_RERRSYNR_SYND2_BIT_NO	(16)
 #define FLEXCAN_RERRSYNR_BE1_MASK	(0x00008000)
 #define FLEXCAN_RERRSYNR_SYND1_MASK	(0x00001F00)
 #define FLEXCAN_RERRSYNR_SYND1_BIT_NO	(8)
-#define FLEXCAN_RERRSYNR_BE0_MASK	(0x00000080) 
-#define FLEXCAN_RERRSYNR_SYND0_MASK	(0x0000001F) 
+#define FLEXCAN_RERRSYNR_BE0_MASK	(0x00000080)
+#define FLEXCAN_RERRSYNR_SYND0_MASK	(0x0000001F)
 #define FLEXCAN_RERRSYNR_SYND0_BIT_NO	(0)
 
 #define FLEXCAN_RERRSYNR_check_BEn_Bit(errsynr,n) (errsynr & FLEXCAN_RERRSYNR_BE##n##_MASK)
@@ -1142,6 +1142,6 @@ typedef volatile uint32_t vuint32_t;
 #define FLEXCAN_ERRSR_FANCEIF_MASK	(0x00040000)
 #define FLEXCAN_ERRSR_HANCEIF_MASK	(0x00080000)
 
- 
+
 /********************************************************************/
 #endif // __KINETIS_FLEXCAN_H