This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm
Table of Contents:
1.INTRODUCTION TO ON-CHIP CLOCK MULTIPLIER
2.THEORY
3.SPECIFICATION
4.TOOLS
5.PRE-LAYOUT DESIGN AND SIMULATION
6.POST-LAYOUT DESIGN AND SIMULATION
7.SCOPE
8.CONCLUSION
9.REFERENCES
1.INTRODUCTION TO ON-CHIP CLOCK MULTIPLIER:
The repository contains simulation files and other relevant files for on-chip clock multiplier using PLL(Fclock-in:5MHZ-12MHz ;Fclock-out:40MHz-100MHz at 1.8V)IP. The goal is to design on-chip clock multiplier using OSU-180nm technology node.The on-chip clock multiplier is present in almost all synchronous processors.
2.THEORY:
A phase-locked loop (PLL) uses a reference frequency(Fclock-in) to generate a multiple of that frequency. A voltage controlled oscillator (VCO) is initially tuned roughly to the range of the desired frequency multiple. The signal from the VCO is divided down using frequency dividers by the multiplication factor. The divided signal and the reference frequency are fed into a phase comparator. The output of the phase comparator is a voltage that is proportional to the phase difference. After passing through a low pass filter and being converted to the proper voltage range, this voltage is fed to the VCO to adjust the frequency. This adjustment increases the frequency as the phase of the VCO's signal lags that of the reference signal and decreases the frequency as the lag decreases (or lead increases). The VCO will stabilize at the desired frequency multiple. This type of PLL is a type of frequency synthesizer.
Modern microprocessors have 2GHz-5GHz clock frequencies whereas quartz oscillator can produce only few MHz ,so to achieve high frequency clock signal from low-frequency clock source we are designing PLL IP block and simulating it in this repository.
3.SPECIFICATION:
| Parameter | Description | Min | Type | Max | Unit | Condition |
|---|---|---|---|---|---|---|
| VDD | Digital supply voltage | 1.8 | V | T=-40 to 150C | ||
| FCLKREF | Reference clock frequency | 5 | 10 | 12.5 | MHz | |
| FCLKOUT | Output clock frequency | 39.7 | 80.91 | 99.81 | MHz | PLL mode, T=27C, VDD=1.8 |
| FCLKOUT | Output clock frequency | MHz | VCO mode, T=27C, VDD=1.8 | |||
| DC | Duty Cycle | 48 | 52 | % | T=-40 to 150C | |
| IBCP | Bias current for VCO | uA | ||||
| VVCO | Oscillatror control input voltage | .557 | 0.62 | V | Vin_vco = 0V at t = 0 (.uic) | |
| JRMS | Jitter (rms) | future work | ps | PLL mode, FCLKREF = 10MHz | ||
| TSET | Settling Time | 5.2 | 5 | 4.6 | us | start from EN_CP and report 2 values; one at FCLKOUT=40MHz and one at FCLKOUT=100MHz |
| CL | Load Capacitance | pF | ||||
| IDDA | Analog Supply current | ua | VVCO=0.8V, VCO mode | |||
| IDDA | Analog Supply current | ua | FCLKREF=10MHz, PLL mode | |||
| IDDA | Analog Supply current | pa | EN_VCO=0, EN_CP=0, FCLKREF=0 | |||
| IDDD | Digital Supply Current | uA | VVCO=0.8V, VCO mode | |||
| IDDD | Digital Supply Current | uA | FCLKREF=10MHz, PLL mode | |||
| IDDD | Digital Supply Current | uA | EN_VCO=0, EN_CP=0, FCLKREF=0 |
4.TOOLS:
The design has been developed using open souce CAD tools .They are:
5.PRE-LAYOUT DESIGN AND SIMULATION:
1.Installl tools
2.Circuit design
3.Netlist extraction
4.Netlist modification for NGSPICE
5.Run
Phase-detector : Based on the feedback from the frequency divider it creates two signals ,up and down which are given to the charge-pump
Charge pump : Charge-pump consists of power MOSFETS it helps in better charging of the capacitors present in the next stage which is a LPF
LPF : LPF is used for smoothning the waveform and get a dc value
MUX : Here MUX is used to select between VCO only mode or PLL
VCO : VCO is used to get the output frequency based on the input DC value
Frequency divider :Here a basic D-Filp-flop based counter is used to get frequency division
Operation of feedback-loop control
As shown above we consider a second-order feed back systesm , the response can be as shown below based on location of poles
For PLL we should obtain a critically damped response as it has less oscillations and its fast.
NETLIST FROM ESIM
NETLIST FOR NGSPICE
RUNNING NGSPICE IN TERMINAL
PHASE DETECTOR
RUNNING IN NGSPICE
Simulation results:
6.POST-LAYOUT DESIGN AND SIMULATION:
1.Phase Frequency Detector
2.2-1 MUX
3.FREQUENCY DIVIDE BY 8
4.PLL
7.SCOPE:
1.Porting this IP on lower technology nodes using advance PDK's where capacitor fabrication is realizable
2.Area Efficient Design Improvements.
3.Improvements for Power Reduction.
4.Improvements of accuracy, jitter & dead zone.
8.CONCLUSION:
I have learnt the flow of designing a PLL and how to design a system from lower block to higher blocks.
9.REFERENCES:
1.https://github.com/parasgidd/avsdpll_3v3
2.VLSI system design pvt ltd tutorial sessions