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conv_ops_float.cc
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conv_ops_float.cc
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/* Copyright 2023 The TensorFlow Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
==============================================================================*/
// See docs in ../ops/nn_ops.cc.
#include "tensorflow/core/kernels/conv_ops_impl.h"
namespace tensorflow {
typedef Eigen::ThreadPoolDevice CPUDevice;
typedef Eigen::GpuDevice GPUDevice;
// Conditionally launches DeepConv operation based on convolution parameters.
template <>
class LaunchDeepConvOp<CPUDevice, float> {
public:
static bool Run(OpKernelContext* ctx, const Tensor& input,
const Tensor& filter, int batch, int input_rows,
int input_cols, int in_depth, int filter_rows,
int filter_cols, int pad_rows, int pad_cols, int out_rows,
int out_cols, int out_depth, int dilation_rows,
int dilation_cols, int stride_rows, int stride_cols,
Tensor* output, TensorFormat data_format) {
if (data_format != FORMAT_NHWC || dilation_rows != 1 ||
dilation_cols != 1 ||
!CanUseDeepConv2D(stride_rows, stride_cols, filter_rows, filter_cols,
in_depth, out_depth, out_rows, out_cols)) {
return false;
}
Conv2DArgs args;
args.batch = batch;
args.in_rows = input_rows;
args.in_cols = input_cols;
args.in_depth = in_depth;
args.filter_rows = filter_rows;
args.filter_cols = filter_cols;
args.pad_rows = pad_rows;
args.pad_cols = pad_cols;
args.out_rows = out_rows;
args.out_cols = out_cols;
args.out_depth = out_depth;
auto input_ptr = input.template flat<float>().data();
auto filter_ptr = filter.template flat<float>().data();
auto output_ptr = output->template flat<float>().data();
functor::DeepConv2D<CPUDevice, float>()(ctx, args, input_ptr, filter_ptr,
output_ptr);
return true;
}
};
// Explicit instantiation.
template struct LaunchConv2DOp<CPUDevice, float>;
template struct Conv2DOp<CPUDevice, float>;
// If we're using the alternative GEMM-based implementation of Conv2D for the
// CPU implementation, don't register this EigenTensor-based version.
#if !defined(USE_GEMM_FOR_CONV)
REGISTER_KERNEL_BUILDER(
Name("Conv2D").Device(DEVICE_CPU).TypeConstraint<float>("T"),
Conv2DOp<CPUDevice, float>);
#endif // USE_GEMM_FOR_CONV
REGISTER_KERNEL_BUILDER(
Name("Conv").Device(DEVICE_CPU).TypeConstraint<float>("T"),
ConvOp<CPUDevice, float>);
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
// Forward declarations of the functor specializations for GPU.
namespace functor {
#define DECLARE_GPU_SPEC(T) \
template <> \
void SpatialConvolution<GPUDevice, T>::operator()( \
const GPUDevice& d, typename TTypes<T, 4>::Tensor output, \
typename TTypes<T, 4>::ConstTensor input, \
typename TTypes<T, 4>::ConstTensor filter, int row_stride, \
int col_stride, int row_dilation, int col_dilation, \
const Eigen::PaddingType& padding, \
const Eigen::NoOpOutputKernel& output_kernel); \
template <> \
void SpatialConvolution<GPUDevice, T>::operator()( \
const GPUDevice& d, typename TTypes<T, 4>::Tensor output, \
typename TTypes<T, 4>::ConstTensor input, \
typename TTypes<T, 4>::ConstTensor filter, int row_stride, \
int col_stride, int row_dilation, int col_dilation, int padding_top, \
int padding_bottom, int padding_left, int padding_right, \
const Eigen::NoOpOutputKernel& output_kernel); \
extern template struct SpatialConvolution<GPUDevice, T>; \
template <> \
void MatMulConvFunctor<GPUDevice, T>::operator()( \
const GPUDevice& d, typename TTypes<T, 2>::Tensor out, \
typename TTypes<T, 2>::ConstTensor in0, \
typename TTypes<T, 2>::ConstTensor in1, \
const Eigen::array<Eigen::IndexPair<Eigen::DenseIndex>, 1>& dim_pair, \
const Eigen::NoOpOutputKernel& output_kernel); \
extern template struct MatMulConvFunctor<GPUDevice, T>; \
template <> \
void TransformFilter<GPUDevice, T, int, 4>::operator()( \
const GPUDevice& d, FilterTensorFormat dst_filter_format, \
typename TTypes<T, 4, int>::ConstTensor in, \
typename TTypes<T, 4, int>::Tensor out); \
extern template struct TransformFilter<GPUDevice, T, int, 4>; \
template <> \
void TransformFilter<GPUDevice, T, int, 5>::operator()( \
const GPUDevice& d, FilterTensorFormat dst_filter_format, \
typename TTypes<T, 5, int>::ConstTensor in, \
typename TTypes<T, 5, int>::Tensor out); \
extern template struct TransformFilter<GPUDevice, T, int, 5>; \
template <> \
void PadInput<GPUDevice, T, int, 4>::operator()( \
const GPUDevice& d, typename TTypes<T, 4, int>::ConstTensor in, \
const std::array<int, 2>& padding_left, \
const std::array<int, 2>& padding_right, \
typename TTypes<T, 4, int>::Tensor out, TensorFormat data_format, \
const T& padding_value); \
extern template struct PadInput<GPUDevice, T, int, 4>; \
template <> \
void PadInput<GPUDevice, T, int, 5>::operator()( \
const GPUDevice& d, typename TTypes<T, 5, int>::ConstTensor in, \
const std::array<int, 3>& padding_left, \
const std::array<int, 3>& padding_right, \
typename TTypes<T, 5, int>::Tensor out, TensorFormat data_format, \
const T& padding_value); \
extern template struct PadInput<GPUDevice, T, int, 5>
DECLARE_GPU_SPEC(float);
#undef DECLARE_GPU_SPEC
} // namespace functor
// Registration of the GPU implementations.
REGISTER_KERNEL_BUILDER(
Name("Conv2D").Device(DEVICE_GPU).TypeConstraint<float>("T"),
Conv2DOp<GPUDevice, float>);
REGISTER_KERNEL_BUILDER(
Name("Conv").Device(DEVICE_GPU).TypeConstraint<float>("T"),
ConvOp<GPUDevice, float>);
// Explicit instantiation.
template struct LaunchConv2DOp<GPUDevice, float>;
template struct LaunchConvOp<GPUDevice, float>;
#endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM
} // namespace tensorflow