-
Notifications
You must be signed in to change notification settings - Fork 74k
/
sequence_ops.cc
221 lines (190 loc) · 8.77 KB
/
sequence_ops.cc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
/* Copyright 2015 The TensorFlow Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
==============================================================================*/
// See docs in ../ops/math_ops.cc.
#include "tensorflow/core/kernels/sequence_ops.h"
#include <cmath>
#include "tensorflow/core/framework/op_kernel.h"
#include "tensorflow/core/framework/op_requires.h"
#include "tensorflow/core/framework/register_types.h"
#include "tensorflow/core/framework/tensor.h"
#include "tensorflow/core/framework/tensor_shape.h"
#include "tensorflow/core/framework/types.h"
namespace tensorflow {
using CPUDevice = Eigen::ThreadPoolDevice;
using GPUDevice = Eigen::GpuDevice;
namespace functor {
template <typename T>
struct RangeFunctor<CPUDevice, T> {
void operator()(OpKernelContext* context, int64_t size, T start, T delta,
typename TTypes<T>::Flat output) const {
(void)context;
for (int64_t i = 0; i < size; ++i) {
output(i) = start + static_cast<T>(i) * delta;
}
}
};
} // namespace functor
template <typename Device, typename T>
class RangeOp : public OpKernel {
public:
explicit RangeOp(OpKernelConstruction* context) : OpKernel(context) {}
void Compute(OpKernelContext* context) override {
const Tensor& start_in = context->input(0);
const Tensor& limit_in = context->input(1);
const Tensor& delta_in = context->input(2);
// TODO(rmlarsen): Disallow legacy use of length-1 vectors as scalars.
OP_REQUIRES(context,
TensorShapeUtils::IsScalar(start_in.shape()) ||
(TensorShapeUtils::IsVector(start_in.shape()) &&
start_in.shape().dim_size(0) == 1),
errors::InvalidArgument("start must be a scalar, not shape ",
start_in.shape().DebugString()));
OP_REQUIRES(context,
TensorShapeUtils::IsScalar(limit_in.shape()) ||
(TensorShapeUtils::IsVector(limit_in.shape()) &&
limit_in.shape().dim_size(0) == 1),
errors::InvalidArgument("limit must be a scalar, not shape ",
limit_in.shape().DebugString()));
OP_REQUIRES(context,
TensorShapeUtils::IsScalar(delta_in.shape()) ||
(TensorShapeUtils::IsVector(delta_in.shape()) &&
delta_in.shape().dim_size(0) == 1),
errors::InvalidArgument("delta must be a scalar, not shape ",
delta_in.shape().DebugString()));
const T start = start_in.scalar<T>()();
const T limit = limit_in.scalar<T>()();
const T delta = delta_in.scalar<T>()();
OP_REQUIRES(context, delta != 0,
errors::InvalidArgument("Requires delta != 0: ", delta));
if (delta > 0) {
OP_REQUIRES(
context, start <= limit,
errors::InvalidArgument(
"Requires start <= limit when delta > 0: ", start, "/", limit));
} else {
OP_REQUIRES(
context, start >= limit,
errors::InvalidArgument(
"Requires start >= limit when delta < 0: ", start, "/", limit));
}
int64_t size;
if (std::is_integral<T>::value) {
size = Eigen::divup(Eigen::numext::abs(limit - start),
Eigen::numext::abs(delta));
} else {
auto size_auto =
Eigen::numext::ceil(Eigen::numext::abs((limit - start) / delta));
OP_REQUIRES(
context, size_auto <= std::numeric_limits<int64_t>::max(),
errors::InvalidArgument("Requires ((limit - start) / delta) <= ",
std::numeric_limits<int64_t>::max()));
size = static_cast<int64_t>(size_auto);
}
TensorShape shape;
OP_REQUIRES_OK(context, shape.AddDimWithStatus(size));
Tensor* out = nullptr;
OP_REQUIRES_OK(context, context->allocate_output(0, shape, &out));
if (size == 0) return;
auto flat = out->flat<T>();
functor::RangeFunctor<Device, T>()(context, size, start, delta, flat);
}
};
#define REGISTER_KERNEL(DEV, DEV_TYPE, TYPE) \
REGISTER_KERNEL_BUILDER(Name("Range") \
.Device(DEV) \
.HostMemory("start") \
.HostMemory("limit") \
.HostMemory("delta") \
.TypeConstraint<TYPE>("Tidx"), \
RangeOp<DEV_TYPE, TYPE>);
#define REGISTER_CPU_KERNEL(T) REGISTER_KERNEL(DEVICE_CPU, CPUDevice, T)
#define REGISTER_GPU_KERNEL(T) REGISTER_KERNEL(DEVICE_GPU, GPUDevice, T)
TF_CALL_float(REGISTER_CPU_KERNEL);
TF_CALL_double(REGISTER_CPU_KERNEL);
TF_CALL_int32(REGISTER_CPU_KERNEL);
TF_CALL_int64(REGISTER_CPU_KERNEL);
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
TF_CALL_float(REGISTER_GPU_KERNEL);
TF_CALL_double(REGISTER_GPU_KERNEL);
TF_CALL_int64(REGISTER_GPU_KERNEL);
#endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM
// Special case to execute int32 on the host with host output.
REGISTER_KERNEL_BUILDER(Name("Range")
.Device(DEVICE_DEFAULT)
.HostMemory("start")
.HostMemory("limit")
.HostMemory("delta")
.HostMemory("output")
.TypeConstraint<int32_t>("Tidx"),
RangeOp<CPUDevice, int32_t>);
#undef REGISTER_KERNEL
#undef REGISTER_CPU_KERNEL
#undef REGISTER_GPU_KERNEL
template <typename T, typename Tnum>
class LinSpaceOp : public OpKernel {
public:
explicit LinSpaceOp(OpKernelConstruction* context) : OpKernel(context) {}
void Compute(OpKernelContext* context) override {
const Tensor& start_in = context->input(0);
const Tensor& stop_in = context->input(1);
const Tensor& num_in = context->input(2);
OP_REQUIRES(context, TensorShapeUtils::IsScalar(start_in.shape()),
errors::InvalidArgument("start must be a scalar, not shape ",
start_in.shape().DebugString()));
OP_REQUIRES(context, TensorShapeUtils::IsScalar(stop_in.shape()),
errors::InvalidArgument("stop must be a scalar, not shape ",
stop_in.shape().DebugString()));
OP_REQUIRES(context, TensorShapeUtils::IsScalar(num_in.shape()),
errors::InvalidArgument("num must be a scalar, not shape ",
num_in.shape().DebugString()));
const T start = start_in.scalar<T>()();
const T stop = stop_in.scalar<T>()();
const Tnum num = num_in.scalar<Tnum>()();
OP_REQUIRES(context, num > 0,
errors::InvalidArgument("Requires num > 0: ", num));
Tensor* out = nullptr;
OP_REQUIRES_OK(context,
context->allocate_output(0, TensorShape({num}), &out));
auto flat = out->flat<T>();
flat(0) = start;
if (num > 1) {
const T step = (stop - start) / (num - 1);
for (Tnum i = 1; i < num - 1; ++i) flat(i) = start + step * i;
// Ensure final value == stop; float arithmetic won't guarantee this.
flat(num - 1) = stop;
}
}
};
#define REGISTER_KERNEL(DEV, T, Tidx) \
REGISTER_KERNEL_BUILDER(Name("LinSpace") \
.Device(DEV) \
.TypeConstraint<T>("T") \
.TypeConstraint<Tidx>("Tidx") \
.HostMemory("start") \
.HostMemory("stop") \
.HostMemory("num") \
.HostMemory("output"), \
LinSpaceOp<T, Tidx>);
#define REGISTER_KERNEL_ALL_NUMS(dev, T) \
REGISTER_KERNEL(dev, T, int32); \
REGISTER_KERNEL(dev, T, int64_t)
#define REGISTER_CPU_KERNEL(T) REGISTER_KERNEL_ALL_NUMS(DEVICE_CPU, T)
TF_CALL_float(REGISTER_CPU_KERNEL);
TF_CALL_double(REGISTER_CPU_KERNEL);
#define REGISTER_DEFAULT_KERNEL(T) REGISTER_KERNEL_ALL_NUMS(DEVICE_DEFAULT, T)
TF_CALL_float(REGISTER_DEFAULT_KERNEL);
TF_CALL_double(REGISTER_DEFAULT_KERNEL);
#undef REGISTER_DEFAULT_KERNEL
#undef REGISTER_CPU_KERNEL
#undef REGISTER_KERNEL_ALL_NUMS
#undef REGISTER_KERNEL
} // namespace tensorflow