[ROCm] Fix for breakage in XLA Conv Op functionality #46219
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The following commit breaks Conv Op functionality (in the XLA backend) for ROCm platform. tensorflow@8684c6b The cause seems to be that the `scratch_size` field in the new `GpuConvDescriptor` is not getting correctly populated in the new MLIR path. It is being used correctly in the convolution runner code. declaration: tensorflow@8684c6b#diff-6453912dbc4ee715a56da9d7b218b52795dea2aa631a482101fc6d58c573d9ccR122-R135 use (get access) in conv runner: tensorflow@8684c6b#diff-a01181d08b28a9c7432f22439622f16725126184283a73822c70b2151098a8adR277 set access in non-MLIR(?) based path: tensorflow@8684c6b#diff-a01181d08b28a9c7432f22439622f16725126184283a73822c70b2151098a8adR450 This commit merely adds the missing "set" in the MLIR based path
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@timshen91 could you take a look? |
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Adding @jurahul who authored the original convolution thunk patch. |
jurahul
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Jan 6, 2021
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The following commit breaks Conv Op functionality (in the XLA backend) for ROCm platform.
8684c6b
The cause seems to be that the
scratch_sizefield in the newGpuConvDescriptoris not getting correctly populated in the new MLIR path. It is being used correctly in the convolution runner code.declaration:
8684c6b#diff-6453912dbc4ee715a56da9d7b218b52795dea2aa631a482101fc6d58c573d9ccR122-R135
use (get access) in conv runner:
8684c6b#diff-a01181d08b28a9c7432f22439622f16725126184283a73822c70b2151098a8adR277
set access in non-MLIR(?) based path:
8684c6b#diff-a01181d08b28a9c7432f22439622f16725126184283a73822c70b2151098a8adR450
This commit merely adds the missing "set" in the MLIR based path
thanks to @ekuznetsov139 for identifying the fix
/cc @chsigg @cheshire @nvining-work