Druid: experiment with 2 bytecodes

tesonep · Apr 13, 2023 · 5fc8398 · 5fc8398
1 parent a4728f9
commit 5fc8398
Showing 1 changed file with 15 additions and 9 deletions.
diff --git a/smalltalksrc/VMMaker/DruidJIT.class.st b/smalltalksrc/VMMaker/DruidJIT.class.st
@@ -26,8 +26,10 @@ DruidJIT class >> bytecodeTable [
 
 	<generated>
 	^ {
-		  { 1. 76. 76. #gen_PushReceiverBytecode. #needsFrameNever:. 1 }.
-		  { 1. 0. 75. #unknownBytecode }.
+		  { 1. 32. 63. #gen_PushLiteralConstantBytecode . #needsFrameNever: . 1}.
+		  { 1. 76. 76. #gen_PushReceiverBytecode . #needsFrameNever: . 1}.
+		  { 1. 0. 31. #unknownBytecode }.
+		  { 1. 64. 75. #unknownBytecode }.
 		  { 1. 77. 223. #unknownBytecode }.
 		  { 2. 224. 247. #unknownBytecode }.
 		  { 3. 248. 255. #unknownBytecode } }
@@ -1495,9 +1497,9 @@ DruidJIT >> gen_PrimitiveDivide [
 	self
 		DivR: ClassReg
 		R: TempReg
-		Quo: SendNumArgsReg
-		Rem: Extra0Reg.
-	self CmpCq: 0 R: Extra0Reg.
+		Quo: Extra0Reg
+		Rem: SendNumArgsReg.
+	self CmpCq: 0 R: SendNumArgsReg.
 	jump4 := self JumpNonZero: 0.
 	self
 		DivR: ClassReg
@@ -1982,13 +1984,16 @@ DruidJIT >> gen_PrimitiveNewWithArg [
 	self
 		DivR: SendNumArgsReg
 		R: Extra2Reg
-		Quo: SendNumArgsReg
-		Rem: Extra2Reg.
+		Quo: Extra2Reg
+		Rem: SendNumArgsReg.
 	self AndCq: 1 R: TempReg.
 	self AddR: TempReg R: ClassReg.
-	self MoveCq: 0 R: Extra2Reg.
+	self MoveCq: 0 R: TempReg.
+	self MoveR: Extra2Reg R: SendNumArgsReg.
+	self MoveR: TempReg R: Extra2Reg.
 	currentBlock := self Label.
 	jump13 jmpTarget: currentBlock.
+	self MoveR: SendNumArgsReg R: TempReg.
 	jump13 := self Jump: 0.
 	currentBlock := self Label.
 	jump6 jmpTarget: currentBlock.
@@ -2022,10 +2027,11 @@ DruidJIT >> gen_PrimitiveNewWithArg [
 	jump4 jmpTarget: currentBlock.
 	self CmpCq: 0 R: Extra1Reg.
 	jump4 := self JumpZero: 0.
+	self MoveR: SendNumArgsReg R: TempReg.
 	self MoveR: Extra0Reg R: Extra2Reg.
 	currentBlock := self Label.
 	jump13 jmpTarget: currentBlock.
-	self MoveR: SendNumArgsReg R: Extra3Reg.
+	self MoveR: TempReg R: Extra3Reg.
 	self MoveR: Extra3Reg Mw: 8 r: SPReg.
 	self MoveR: ClassReg R: Extra3Reg.
 	self MoveR: Extra3Reg Mw: 16 r: SPReg.