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tegra: clemsyn's overclocking patch
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@that1
that1 committed Jul 2, 2013
1 parent 7fc9a0a commit bd8409b
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Showing 5 changed files with 197 additions and 97 deletions.
2 changes: 1 addition & 1 deletion arch/arm/mach-tegra/common.c
View file
Expand Up @@ -104,7 +104,7 @@ static struct board_info pmu_board_info;
static struct board_info display_board_info;
static struct board_info camera_board_info;

static int pmu_core_edp = 1300; /* default 1.2V EDP limit */
static int pmu_core_edp = 1400; /* default 1.2V EDP limit */
static int board_panel_type;
static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;

Expand Down
92 changes: 77 additions & 15 deletions arch/arm/mach-tegra/cpu-tegra.c
View file
Expand Up @@ -51,9 +51,12 @@
#define SYSTEM_NORMAL_MODE (0)
#define SYSTEM_BALANCE_MODE (1)
#define SYSTEM_PWRSAVE_MODE (2)
#define SYSTEM_MODE_END (SYSTEM_PWRSAVE_MODE + 1)
#define SYSTEM_OVERCLOCK_1P5G_MODE (3)
#define SYSTEM_MODE_END (SYSTEM_OVERCLOCK_1P5G_MODE + 1)
#define SYSTEM_PWRSAVE_MODE_MAX_FREQ (1000000)
unsigned int power_mode_table[SYSTEM_MODE_END] = {1000000,1200000,1400000};
#define ASUS_OVERCLOCK

unsigned int power_mode_table[SYSTEM_MODE_END] = {1000000,1200000,1400000,1500000};

#define CAMERA_ENABLE_EMC_MINMIAM_RATE (667000000)
/* tegra throttling and edp governors require frequencies in the table
Expand All @@ -69,6 +72,7 @@ static unsigned long target_cpu_speed[CONFIG_NR_CPUS];
static DEFINE_MUTEX(tegra_cpu_lock);
static bool is_suspended;
static int suspend_index;
static bool edp_enable = 0;
static bool force_policy_max;
int gps_enable=0;

Expand Down Expand Up @@ -255,10 +259,14 @@ static int system_mode_set(const char *arg, const struct kernel_param *kp)
ret = param_set_int(arg, kp);
if (ret == 0) {
printk("system_mode_set system_mode=%u\n",system_mode);
#ifdef ASUS_OVERCLOCK
if( (system_mode<SYSTEM_NORMAL_MODE) || (system_mode>SYSTEM_OVERCLOCK_1P5G_MODE))
system_mode=SYSTEM_NORMAL_MODE;
#else

if((system_mode < SYSTEM_NORMAL_MODE) || (system_mode > SYSTEM_PWRSAVE_MODE))
system_mode = SYSTEM_NORMAL_MODE;

#endif
tegra_cpu_set_speed_cap(NULL);
}

Expand Down Expand Up @@ -332,12 +340,18 @@ module_param_cb(enable_pwr_save, &tegra_pwr_save_ops, &pwr_save, 0644);
else if((system_mode == SYSTEM_NORMAL_MODE) && (requested_speed > power_mode_table[SYSTEM_NORMAL_MODE]))
new_speed = power_mode_table[SYSTEM_NORMAL_MODE];

#ifdef ASUS_OVERCLOCK
else if( (system_mode==SYSTEM_OVERCLOCK_1P5G_MODE ) && ( requested_speed > power_mode_table[SYSTEM_OVERCLOCK_1P5G_MODE] ))
new_speed=power_mode_table[SYSTEM_OVERCLOCK_1P5G_MODE] ;

#endif

return new_speed;
}

static unsigned int cpu_user_cap;

static inline void _cpu_user_cap_set_locked(void)
/*static inline void _cpu_user_cap_set_locked(void)
{
#ifndef CONFIG_TEGRA_CPU_CAP_EXACT_FREQ
if (cpu_user_cap != 0) {
Expand All @@ -361,7 +375,7 @@ void tegra_cpu_user_cap_set(unsigned int speed_khz)
_cpu_user_cap_set_locked();
mutex_unlock(&tegra_cpu_lock);
}
}*/

static int cpu_user_cap_set(const char *arg, const struct kernel_param *kp)
{
Expand All @@ -370,11 +384,25 @@ static int cpu_user_cap_set(const char *arg, const struct kernel_param *kp)
mutex_lock(&tegra_cpu_lock);

ret = param_set_uint(arg, kp);
if (ret == 0)
_cpu_user_cap_set_locked();
if (ret == 0) {
#ifndef CONFIG_TEGRA_CPU_CAP_EXACT_FREQ
if (cpu_user_cap != 0) {
int i;
for (i = 0; freq_table[i].frequency !=
CPUFREQ_TABLE_END; i++) {
if (freq_table[i].frequency > cpu_user_cap)
break;
}
i = (i == 0) ? 0 : i - 1;
cpu_user_cap = freq_table[i].frequency;
}
#endif
tegra_cpu_set_speed_cap(NULL);
}

mutex_unlock(&tegra_cpu_lock);
return ret;

}

static int cpu_user_cap_get(char *buffer, const struct kernel_param *kp)
Expand Down Expand Up @@ -474,6 +502,14 @@ int tegra_edp_update_thermal_zone(int temperature)
int nlimits = cpu_edp_limits_size;
int index;

#ifdef ASUS_OVERCLOCK
if (temperature >= 70) {
edp_enable = 1;
} else {
edp_enable = 0;
}
#endif

if (!cpu_edp_limits)
return -EINVAL;

Expand Down Expand Up @@ -680,10 +716,11 @@ module_param_cb(pwr_cap_limit_4, &pwr_cap_ops, &pwr_cap_limits[3], 0644);
static int pwr_mode_table_debugfs_show(struct seq_file *s, void *data)
{
seq_printf(s, "-- CPU power mode table --\n");
seq_printf(s, "Power Saving=%u \n Balanced=%u \n Normal=%u \n \n",
seq_printf(s, "Power Saving=%u \n Balanced=%u \n Normal=%u \n Over 1=%u\n",
power_mode_table[2],
power_mode_table[1],
power_mode_table[0]);
power_mode_table[0],
power_mode_table[3]);
return 0;
}

Expand Down Expand Up @@ -746,9 +783,9 @@ static int __init tegra_cpu_debug_init(void)

if (tegra_edp_debug_init(cpu_tegra_debugfs_root))
goto err_out;
if (!debugfs_create_file("pwr_mode_table", 0644, cpu_tegra_debugfs_root,
NULL, &pwr_mode_table_debugfs_fops))
goto err_out;
// if (!debugfs_create_file("pwr_mode_table", 0644, cpu_tegra_debugfs_root,
// NULL, &pwr_mode_table_debugfs_fops))
//goto err_out;

return 0;

Expand Down Expand Up @@ -919,7 +956,19 @@ int tegra_suspended_target(unsigned int target_freq)

/* apply only "hard" caps */
new_speed = tegra_throttle_governor_speed(new_speed);
#ifdef ASUS_OVERCLOCK
if(system_mode == SYSTEM_OVERCLOCK_1P5G_MODE) {
if(edp_enable) {
pr_info("%s : EDP enable\n", __func__);
new_speed = edp_governor_speed(new_speed);
}
} else {
new_speed = edp_governor_speed(new_speed);
}
#else
new_speed = edp_governor_speed(new_speed);
#endif


return tegra_update_cpu_speed(new_speed);
}
Expand All @@ -938,7 +987,18 @@ int tegra_cpu_late_resume_set_speed_cap(int speed)

new_speed = ASUS_governor_speed(new_speed);
new_speed = tegra_throttle_governor_speed(new_speed);
#ifdef ASUS_OVERCLOCK
if(system_mode == SYSTEM_OVERCLOCK_1P5G_MODE){
if(edp_enable){
pr_info("%s : EDP enable\n", __func__);
new_speed = edp_governor_speed(new_speed);
}
}else
new_speed = edp_governor_speed(new_speed);
#else
new_speed = edp_governor_speed(new_speed);
#endif


printk("tegra_cpu_late_resume_set_speed_cap new_speed =%u\n",new_speed );
ret = tegra_update_cpu_speed(new_speed);
Expand Down Expand Up @@ -1061,9 +1121,11 @@ static struct notifier_block tegra_cpu_pm_notifier = {

void rebuild_max_freq_table(unsigned int max_rate)
{
power_mode_table[SYSTEM_NORMAL_MODE] = max_rate;
power_mode_table[SYSTEM_BALANCE_MODE] = max_rate - 200000;
power_mode_table[SYSTEM_NORMAL_MODE] = 1500000;
power_mode_table[SYSTEM_BALANCE_MODE] = 1300000;
power_mode_table[SYSTEM_PWRSAVE_MODE] = SYSTEM_PWRSAVE_MODE_MAX_FREQ;
power_mode_table[SYSTEM_OVERCLOCK_1P5G_MODE]=1800000;

}

static int tegra_cpu_init(struct cpufreq_policy *policy)
Expand All @@ -1090,7 +1152,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
target_cpu_speed[policy->cpu] = policy->cur;

/* FIXME: what's the actual transition time? */
policy->cpuinfo.transition_latency = 300 * 1000;
policy->cpuinfo.transition_latency = 40 * 1000;

policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
cpumask_copy(policy->related_cpus, cpu_possible_mask);
Expand Down
64 changes: 50 additions & 14 deletions arch/arm/mach-tegra/tegra3_clocks.c
View file
Expand Up @@ -3335,6 +3335,14 @@ static struct clk tegra_pll_ref = {
};

static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {

{ 12000000, 1400000000, 700, 6, 1, 8},
{ 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
{ 16800000, 1400000000, 583, 7, 1, 8},
{ 19200000, 1400000000, 533, 8, 1, 8},
{ 26000000, 1400000000, 700, 13, 1, 8},


{ 12000000, 1200000000, 600, 6, 1, 8},
{ 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
{ 16800000, 1200000000, 500, 7, 1, 8},
Expand Down Expand Up @@ -3663,6 +3671,14 @@ static struct clk tegra_pll_u = {
};

static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {

/*1.8 GHz */
{ 12000000, 1800000000, 850, 6, 1, 8},
{ 13000000, 1800000000, 915, 7, 1, 8},
{ 16800000, 1800000000, 708, 7, 1, 8},
{ 19200000, 1800000000, 885, 10, 1, 8},
{ 26000000, 1800000000, 900, 13, 1, 8},

/* 1.7 GHz */
{ 12000000, 1700000000, 850, 6, 1, 8},
{ 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
Expand Down Expand Up @@ -3728,14 +3744,14 @@ static struct clk tegra_pll_x = {
.ops = &tegra_pll_ops,
.reg = 0xe0,
.parent = &tegra_pll_ref,
.max_rate = 1700000000,
.max_rate = 1800000000,
.u.pll = {
.input_min = 2000000,
.input_max = 31000000,
.cf_min = 1000000,
.cf_max = 6000000,
.vco_min = 20000000,
.vco_max = 1700000000,
.vco_max = 1800000000,
.freq_table = tegra_pll_x_freq_table,
.lock_delay = 300,
},
Expand Down Expand Up @@ -4013,7 +4029,7 @@ static struct clk tegra_clk_cclk_g = {
.inputs = mux_cclk_g,
.reg = 0x368,
.ops = &tegra_super_ops,
.max_rate = 1700000000,
.max_rate = 1800000000,
};

static struct clk tegra_clk_cclk_lp = {
Expand All @@ -4038,7 +4054,7 @@ static struct clk tegra_clk_virtual_cpu_g = {
.name = "cpu_g",
.parent = &tegra_clk_cclk_g,
.ops = &tegra_cpu_ops,
.max_rate = 1700000000,
.max_rate = 1800000000,
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p,
Expand Down Expand Up @@ -4068,7 +4084,7 @@ static struct clk tegra_clk_cpu_cmplx = {
.name = "cpu",
.inputs = mux_cpu_cmplx,
.ops = &tegra_cpu_cmplx_ops,
.max_rate = 1700000000,
.max_rate = 1800000000,
};

static struct clk tegra_clk_cop = {
Expand Down Expand Up @@ -4380,12 +4396,12 @@ struct clk tegra_list_clks[] = {
PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 650000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* max rate ??? */
PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 65000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
PERIPH_CLK("i2c1", "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c2", "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c3", "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
Expand All @@ -4408,12 +4424,12 @@ struct clk tegra_list_clks[] = {
PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 470000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 650000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 650000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 650000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 650000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 650000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 325000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
Expand All @@ -4440,7 +4456,7 @@ struct clk tegra_list_clks[] = {
PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("se", "se", NULL, 127, 0x42c, 625000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
PERIPH_CLK("se", "se", NULL, 127, 0x42c, 650000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 108000000, mux_pllp_clkm, MUX | DIV_U71),

SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
Expand Down Expand Up @@ -4870,13 +4886,33 @@ static struct cpufreq_frequency_table freq_table_1p7GHz[] = {
{15, CPUFREQ_TABLE_END },
};

static struct cpufreq_frequency_table freq_table_1p8GHz[] = {
{ 0, 51000 },
{ 1, 102000 },
{ 2, 204000 },
{ 3, 370000 },
{ 4, 475000 },
{ 5, 620000 },
{ 6, 760000 },
{ 7, 910000 },
{ 8, 1150000 },
{ 9, 1300000 },
{10, 1400000 },
{11, 1500000 },
{12, 1600000 },
{13, 1700000 },
{14, 1800000 },
{15, CPUFREQ_TABLE_END },
};

static struct tegra_cpufreq_table_data cpufreq_tables[] = {
{ freq_table_300MHz, 0, 1 },
{ freq_table_1p0GHz, 2, 8 },
{ freq_table_1p3GHz, 2, 10 },
{ freq_table_1p4GHz, 2, 11 },
{ freq_table_1p5GHz, 2, 12 },
{ freq_table_1p7GHz, 2, 12 },
{ freq_table_1p8GHz, 2, 12 },
};

static int clip_cpu_rate_limits(
Expand Down

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