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  1. AXI_Slave_Interface AXI_Slave_Interface Public

    A Slave interface for DRAM

    Verilog 9 3

  2. AXI_APB_Bridge AXI_APB_Bridge Public

    Started a new repo for AXI to APB bridge

    Verilog 7

  3. facebookapp facebookapp Public

    my first facebook app

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  4. Major_Project_Files Major_Project_Files Public

    Soc_Design

  5. DMA_Controller DMA_Controller Public

    Another controller project

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  6. AXI_RAM_SLAVE AXI_RAM_SLAVE Public

    A slave interface for RAM