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Add parameter support to all currently-supported simulators
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@alexforencich
alexforencich committed Oct 24, 2020
1 parent 6f167d7 commit 89adfa8
Showing 1 changed file with 54 additions and 7 deletions.
61 changes: 54 additions & 7 deletions cocotb_test/simulator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -366,6 +366,13 @@ def get_define_commands(self, defines):

return defines_cmd

def get_parameter_commands(self, parameters):
parameters_cmd = []
for name, value in parameters.items():
parameters_cmd.append("-g" + name + "=" + str(value))

return parameters_cmd

def build_command(self):

self.rtl_library = self.toplevel
Expand Down Expand Up @@ -410,7 +417,7 @@ def build_command(self):
EXT_NAME=as_tcl_value(
"cocotb_init {}".format(os.path.join(self.lib_dir, "libcocotbfli_modelsim." + self.lib_ext))
),
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in self.simulation_args),
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in (self.simulation_args + self.get_parameter_commands(self.parameters))),
)

if self.verilog_sources:
Expand All @@ -422,7 +429,7 @@ def build_command(self):
RTL_LIBRARY=as_tcl_value(self.rtl_library),
TOPLEVEL=as_tcl_value(self.toplevel),
EXT_NAME=as_tcl_value(os.path.join(self.lib_dir, "libcocotbvpi_modelsim." + self.lib_ext)),
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in self.simulation_args),
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in (self.simulation_args + self.get_parameter_commands(self.parameters))),
PLUS_ARGS=" ".join(as_tcl_value(v) for v in self.plus_args),
)

Expand Down Expand Up @@ -461,6 +468,14 @@ def get_define_commands(self, defines):

return defines_cmd

def get_parameter_commands(self, parameters):
parameters_cmd = []
for name, value in parameters.items():
parameters_cmd.append("-defparam")
parameters_cmd.append("\"" + self.toplevel + "." + name + "=" + str(value) + "\"")

return parameters_cmd

def build_command(self):

out_file = os.path.join(self.sim_dir, "INCA_libs", "history")
Expand All @@ -486,6 +501,7 @@ def build_command(self):
]
+ self.get_define_commands(self.defines)
+ self.get_include_commands(self.includes)
+ self.get_parameter_commands(self.parameters)
+ self.compile_args
+ self.verilog_sources
+ self.vhdl_sources
Expand All @@ -496,7 +512,7 @@ def build_command(self):
self.logger.warning("Skipping compilation:" + out_file)

if not self.compile_only:
cmd_run = ["irun", "-64", "-R", ("-gui" if self.gui else "")] + self.simulation_args + self.plus_args
cmd_run = ["irun", "-64", "-R", ("-gui" if self.gui else "")] + self.simulation_args + self.get_parameter_commands(self.parameters) + self.plus_args
cmd.append(cmd_run)

return cmd
Expand Down Expand Up @@ -524,6 +540,14 @@ def get_define_commands(self, defines):

return defines_cmd

def get_parameter_commands(self, parameters):
parameters_cmd = []
for name, value in parameters.items():
parameters_cmd.append("-defparam")
parameters_cmd.append("\"" + self.toplevel + "." + name + "=" + str(value) + "\"")

return parameters_cmd

def build_command(self):

out_file = os.path.join(self.sim_dir, "INCA_libs", "history")
Expand All @@ -549,6 +573,7 @@ def build_command(self):
]
+ self.get_define_commands(self.defines)
+ self.get_include_commands(self.includes)
+ self.get_parameter_commands(self.parameters)
+ self.compile_args
+ self.verilog_sources
+ self.vhdl_sources
Expand All @@ -559,7 +584,7 @@ def build_command(self):
self.logger.warning("Skipping compilation:" + out_file)

if not self.compile_only:
cmd_run = ["xrun", "-64", "-R", ("-gui" if self.gui else "")] + self.simulation_args + self.plus_args
cmd_run = ["xrun", "-64", "-R", ("-gui" if self.gui else "")] + self.simulation_args + self.get_parameter_commands(self.parameters) + self.plus_args
cmd.append(cmd_run)

return cmd
Expand All @@ -580,6 +605,13 @@ def get_define_commands(self, defines):

return defines_cmd

def get_parameter_commands(self, parameters):
parameters_cmd = []
for name, value in parameters.items():
parameters_cmd.append("-pvalue+" + self.toplevel + "/" + name + "=" + str(value))

return parameters_cmd

def build_command(self):

pli_cmd = "acc+=rw,wn:*"
Expand All @@ -605,6 +637,7 @@ def build_command(self):
]
+ self.get_define_commands(self.defines)
+ self.get_include_commands(self.includes)
+ self.get_parameter_commands(self.parameters)
+ self.compile_args
+ self.verilog_sources
)
Expand Down Expand Up @@ -635,6 +668,13 @@ def get_define_commands(self, defines):
defines_cmd.append("-D")
defines_cmd.append(define)

def get_parameter_commands(self, parameters):
parameters_cmd = []
for name, value in parameters.items():
parameters_cmd.append("-g" + name + "=" + str(value))

return parameters_cmd

def build_command(self):

cmd = []
Expand All @@ -653,7 +693,7 @@ def build_command(self):
"-r",
self.toplevel,
"--vpi=" + os.path.join(self.lib_dir, "libcocotbvpi_ghdl." + self.lib_ext),
] + self.simulation_args
] + self.simulation_args + self.get_parameter_commands(self.parameters)

if not self.compile_only:
cmd.append(cmd_run)
Expand All @@ -676,6 +716,13 @@ def get_define_commands(self, defines):

return defines_cmd

def get_parameter_commands(self, parameters):
parameters_cmd = []
for name, value in parameters.items():
parameters_cmd.append("-g" + name + "=" + str(value))

return parameters_cmd

def build_command(self):

self.rtl_library = self.toplevel
Expand Down Expand Up @@ -712,7 +759,7 @@ def build_command(self):
RTL_LIBRARY=as_tcl_value(self.rtl_library),
TOPLEVEL=as_tcl_value(self.toplevel),
EXT_NAME=as_tcl_value(os.path.join(self.lib_dir, "libcocotbvhpi_aldec")),
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in self.simulation_args),
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in (self.simulation_args + self.get_parameter_commands(self.parameters))),
)
if self.verilog_sources:
self.env["GPI_EXTRA"] = "cocotbvpi_aldec:cocotbvpi_entry_point"
Expand All @@ -721,7 +768,7 @@ def build_command(self):
RTL_LIBRARY=as_tcl_value(self.rtl_library),
TOPLEVEL=as_tcl_value(self.toplevel),
EXT_NAME=as_tcl_value(os.path.join(self.lib_dir, "libcocotbvpi_aldec")),
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in self.simulation_args),
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in (self.simulation_args + self.get_parameter_commands(self.parameters))),
PLUS_ARGS=" ".join(as_tcl_value(v) for v in self.plus_args),
)
if self.vhdl_sources:
Expand Down

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