-
Notifications
You must be signed in to change notification settings - Fork 128
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
ASoC: SOF: Intel: follow recommended sequences to retrieve DPIB information #3143
Conversation
we use 'bus->use_posbuf && bus->posbuf.addr' in hda_dsp_ctrl_init_chip(), use the same for hda_dsp_ctrl_stop_chip() Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
The existing code is inconsistent, we should only enable DPIB if the 'use_posbuf' field is true. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
The code inherited from the Skylake driver does not seem to follow any known hardware recommendations. The only two recommended options are a) use DPIB registers if VC1 traffic is not allowed b) use DPIB DDR update if VC1 traffic is used In all of SOF-based updated, VC1 is not supported so we can 'safely' move to using DPIB registers only. This patch keeps the legacy code, in case there was an undocumented issue lost to history, and adds the DPIB DDR update for additional debug. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
@naveen-manohar FYI. possible to test this patch set at some point with dmic and simulation? |
Thanks @juimonen , shall check post I get official Simics Release with fixes for DMIC. Thanks |
|
if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) | ||
bus->use_posbuf = 0; | ||
else | ||
bus->use_posbuf = 1; |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
this is a change in behaviour for the current mode, is this intended?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
the commit message is pretty clear, no?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
The series does what it tells it does, but I'm not sure if we are missing something around the DPLBASE
This is a very intrusive patch coming from an interaction with Intel hardware architects, who mentioned the existing SOF code does not follow recommended sequences. The code in SOF follows the same pattern than the Skylake driver, but the existing work-around does not seem to solve a known problem. Oh well.
This PR adds the recommended sequences, with the selection made by a kernel module parameter to debug any regressions.
Compile-tested only for now, let's see how this works in practice.