ASoC: SOF: use GENMASK and BIT macros wherever possible

sound/soc/sof/intel/byt.c

@@ -57,7 +57,7 @@
 
 #define BYT_PCI_BAR_SIZE	0x200000
 
-#define BYT_PANIC_OFFSET(x)	(((x) & (0xFFFFll << 32)) >> 32)
+#define BYT_PANIC_OFFSET(x)	(((x) & GENMASK_ULL(47, 32)) >> 32)
 
 /*
  * Debug

sound/soc/sof/intel/hda-loader-skl.c

@@ -95,22 +95,24 @@
 
 /* Buffer Descriptor List Lower Base Address */
 #define HDA_CL_SD_BDLPLBA_SHIFT		7
-#define HDA_CL_SD_BDLPLBA_MASK		(0x1ffffff << HDA_CL_SD_BDLPLBA_SHIFT)
+#define HDA_CL_SD_BDLPLBA_MASK		GENMASK(HDA_CL_SD_BDLPLBA_SHIFT + 24,\
+						HDA_CL_SD_BDLPLBA_SHIFT)
 #define HDA_CL_SD_BDLPLBA(x)		\
 	((BDL_ALIGN(lower_32_bits(x)) << HDA_CL_SD_BDLPLBA_SHIFT) & \
 	 HDA_CL_SD_BDLPLBA_MASK)
 
 /* Buffer Descriptor List Upper Base Address */
 #define HDA_CL_SD_BDLPUBA_SHIFT		0
-#define HDA_CL_SD_BDLPUBA_MASK		(0xffffffff << HDA_CL_SD_BDLPUBA_SHIFT)
+#define HDA_CL_SD_BDLPUBA_MASK		GENMASK(HDA_CL_SD_BDLPUBA_SHIFT + 31,\
+						HDA_CL_SD_BDLPUBA_SHIFT)
 #define HDA_CL_SD_BDLPUBA(x)		\
 		((upper_32_bits(x) << HDA_CL_SD_BDLPUBA_SHIFT) & \
 		 HDA_CL_SD_BDLPUBA_MASK)
 
 /* Software Position in Buffer Enable */
 #define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT	0
 #define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK	\
-			(1 << HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT)
+			BIT(HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT)
 
 #define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE(x)	\
 			(((x) << HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & \

sound/soc/sof/intel/hda.h

@@ -49,7 +49,8 @@
 
 #define SOF_HDA_MAX_CAPS		10
 #define SOF_HDA_CAP_ID_OFF		16
-#define SOF_HDA_CAP_ID_MASK		(0xFFF << SOF_HDA_CAP_ID_OFF)
+#define SOF_HDA_CAP_ID_MASK		GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
+						SOF_HDA_CAP_ID_OFF)
 #define SOF_HDA_CAP_NEXT_MASK		0xFFFF
 
 #define SOF_HDA_GTS_CAP_ID			0x1
@@ -129,7 +130,8 @@
 /* Stream Number */
 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT	20
 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
-	(0xf << SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
+	GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
+		SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
 
 #define HDA_DSP_HDA_BAR				0
 #define HDA_DSP_PP_BAR				1

sound/soc/sof/intel/shim.h

@@ -43,56 +43,56 @@
  */
 
 /* CSR / CS */
-#define SHIM_CSR_RST		(0x1 << 1)
-#define SHIM_CSR_SBCS0		(0x1 << 2)
-#define SHIM_CSR_SBCS1		(0x1 << 3)
+#define SHIM_CSR_RST		BIT(1)
+#define SHIM_CSR_SBCS0		BIT(2)
+#define SHIM_CSR_SBCS1		BIT(3)
 #define SHIM_CSR_DCS(x)		((x) << 4)
 #define SHIM_CSR_DCS_MASK	(0x7 << 4)
-#define SHIM_CSR_STALL		(0x1 << 10)
-#define SHIM_CSR_S0IOCS		(0x1 << 21)
-#define SHIM_CSR_S1IOCS		(0x1 << 23)
-#define SHIM_CSR_LPCS		(0x1 << 31)
+#define SHIM_CSR_STALL		BIT(10)
+#define SHIM_CSR_S0IOCS		BIT(21)
+#define SHIM_CSR_S1IOCS		BIT(23)
+#define SHIM_CSR_LPCS		BIT(31)
 #define SHIM_CSR_24MHZ_LPCS \
 	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
 #define SHIM_CSR_24MHZ_NO_LPCS	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
-#define SHIM_BYT_CSR_RST	(0x1 << 0)
-#define SHIM_BYT_CSR_VECTOR_SEL	(0x1 << 1)
-#define SHIM_BYT_CSR_STALL	(0x1 << 2)
-#define SHIM_BYT_CSR_PWAITMODE	(0x1 << 3)
+#define SHIM_BYT_CSR_RST	BIT(0)
+#define SHIM_BYT_CSR_VECTOR_SEL	BIT(1)
+#define SHIM_BYT_CSR_STALL	BIT(2)
+#define SHIM_BYT_CSR_PWAITMODE	BIT(3)
 
 /*  ISRX / ISC */
-#define SHIM_ISRX_BUSY		(0x1 << 1)
-#define SHIM_ISRX_DONE		(0x1 << 0)
-#define SHIM_BYT_ISRX_REQUEST	(0x1 << 1)
+#define SHIM_ISRX_BUSY		BIT(1)
+#define SHIM_ISRX_DONE		BIT(0)
+#define SHIM_BYT_ISRX_REQUEST	BIT(1)
 
 /*  ISRD / ISD */
-#define SHIM_ISRD_BUSY		(0x1 << 1)
-#define SHIM_ISRD_DONE		(0x1 << 0)
+#define SHIM_ISRD_BUSY		BIT(1)
+#define SHIM_ISRD_DONE		BIT(0)
 
 /* IMRX / IMC */
-#define SHIM_IMRX_BUSY		(0x1 << 1)
-#define SHIM_IMRX_DONE		(0x1 << 0)
-#define SHIM_BYT_IMRX_REQUEST	(0x1 << 1)
+#define SHIM_IMRX_BUSY		BIT(1)
+#define SHIM_IMRX_DONE		BIT(0)
+#define SHIM_BYT_IMRX_REQUEST	BIT(1)
 
 /* IMRD / IMD */
-#define SHIM_IMRD_DONE		(0x1 << 0)
-#define SHIM_IMRD_BUSY		(0x1 << 1)
-#define SHIM_IMRD_SSP0		(0x1 << 16)
-#define SHIM_IMRD_DMAC0		(0x1 << 21)
-#define SHIM_IMRD_DMAC1		(0x1 << 22)
+#define SHIM_IMRD_DONE		BIT(0)
+#define SHIM_IMRD_BUSY		BIT(1)
+#define SHIM_IMRD_SSP0		BIT(16)
+#define SHIM_IMRD_DMAC0		BIT(21)
+#define SHIM_IMRD_DMAC1		BIT(22)
 #define SHIM_IMRD_DMAC		(SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
 
 /*  IPCX / IPCC */
-#define	SHIM_IPCX_DONE		(0x1 << 30)
-#define	SHIM_IPCX_BUSY		(0x1 << 31)
-#define SHIM_BYT_IPCX_DONE	((u64)0x1 << 62)
-#define SHIM_BYT_IPCX_BUSY	((u64)0x1 << 63)
+#define	SHIM_IPCX_DONE		BIT(30)
+#define	SHIM_IPCX_BUSY		BIT(31)
+#define SHIM_BYT_IPCX_DONE	BIT_ULL(62)
+#define SHIM_BYT_IPCX_BUSY	BIT_ULL(63)
 
 /*  IPCD */
-#define	SHIM_IPCD_DONE		(0x1 << 30)
-#define	SHIM_IPCD_BUSY		(0x1 << 31)
-#define SHIM_BYT_IPCD_DONE	((u64)0x1 << 62)
-#define SHIM_BYT_IPCD_BUSY	((u64)0x1 << 63)
+#define	SHIM_IPCD_DONE		BIT(30)
+#define	SHIM_IPCD_BUSY		BIT(31)
+#define SHIM_BYT_IPCD_DONE	BIT_ULL(62)
+#define SHIM_BYT_IPCD_BUSY	BIT_ULL(63)
 
 /* CLKCTL */
 #define SHIM_CLKCTL_SMOS(x)	((x) << 24)
@@ -136,9 +136,11 @@
 #define PCI_VDRTCL0_D3PGD		BIT(0)
 #define PCI_VDRTCL0_D3SRAMPGD		BIT(1)
 #define PCI_VDRTCL0_DSRAMPGE_SHIFT	12
-#define PCI_VDRTCL0_DSRAMPGE_MASK	(0xfffff << PCI_VDRTCL0_DSRAMPGE_SHIFT)
+#define PCI_VDRTCL0_DSRAMPGE_MASK	GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
+						PCI_VDRTCL0_DSRAMPGE_SHIFT)
 #define PCI_VDRTCL0_ISRAMPGE_SHIFT	2
-#define PCI_VDRTCL0_ISRAMPGE_MASK	(0x3ff << PCI_VDRTCL0_ISRAMPGE_SHIFT)
+#define PCI_VDRTCL0_ISRAMPGE_MASK	GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
+						PCI_VDRTCL0_ISRAMPGE_SHIFT)
 
 /* VDRTCTL2 */
 #define PCI_VDRTCL2_DCLCGE		BIT(1)