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topology: fix bad parameters in generic dmic dai add #2089

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merged 14 commits into from
Nov 25, 2019
Merged

topology: fix bad parameters in generic dmic dai add #2089

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a438feb
topology: intel-generic-dmic.m4: fix dai parameters
Nov 15, 2019
46afa5a
topology: sof-bdw-codec.m4: add time domain DMA
Nov 15, 2019
13c2de7
topology: sof-cht-nocodec.m4: add time domain DMA
Nov 15, 2019
a8c73ea
topology: sof-cht-rt5682.m4: add time domain DMA
Nov 15, 2019
d542258
topology: sof-byt-codec.m4: add time domain DMA
Nov 15, 2019
5f4aaf4
topology: sof-cht-max98090.m4: add time domain DMA
Nov 15, 2019
e0f67a6
topology: sof-cht-src-50khz-pcm512x.m4: add time domain DMA
Nov 15, 2019
5b9e6f7
topology: sof-imx8qxp-cs42888.m4: add time domain DMA
Nov 15, 2019
b4b66b8
topology: sof-imx8qxp-nocodec-sai.m4: add time domain DMA
Nov 15, 2019
64cf2dc
topology: sof-imx8qxp-nocodec.m4: add time domain DMA
Nov 15, 2019
912459b
topology: sof-imx8qxp-wm8960.m4: add time domain DMA
Nov 15, 2019
6bccee4
topology: sof-cml-rt5682.m4: remove extra parameters
Nov 14, 2019
1ec17c9
topology: sof-bdw-codec.m4: add scheduling dai to media pipe
Nov 15, 2019
6882461
topology: sof-hsw-rt5640.m4: remove topology
Nov 25, 2019
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1 change: 0 additions & 1 deletion tools/topology/CMakeLists.txt
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Expand Up @@ -38,7 +38,6 @@ set(TPLGS
"sof-byt-codec\;sof-byt-rt5682\;-DCODEC=RT5682"
"sof-byt-codec\;sof-byt-da7213\;-DCODEC=DA7213"
"sof-cnl-rt274\;sof-cnl-rt274"
"sof-hsw-rt5640\;sof-hsw-rt5640"
"sof-apl-tdf8532\;sof-apl-tdf8532"
"sof-apl-pcm512x\;sof-apl-pcm512x"
"sof-apl-pcm512x-nohdmi\;sof-apl-pcm512x-nohdmi"
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4 changes: 2 additions & 2 deletions tools/topology/platform/intel/intel-generic-dmic.m4
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Expand Up @@ -46,14 +46,14 @@ dnl deadline, priority, core, time_domain)
DAI_ADD(sof/pipe-dai-capture.m4,
DMIC_PIPELINE_48k_ID, DMIC, 0, dmic01,
concat(`PIPELINE_SINK_', DMIC_PIPELINE_48k_ID), 2, s32le,
1000, 0, 0, 48000, 48000, 48000)
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@plbossart plbossart Nov 12, 2019 •
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those parameters are obviously wrong, but shouldn't we use the TIMER now?
The DMIC is clock master so there's no real benefit in using DMA interrupts here, is there?

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hmm, ok someone needs to jump in here, because I don't know this area.... maybe before the wrong value 16000 something has been just interpreted as != 0 -> so timer?

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@tlauda @lgirdwood see above?

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@juimonen these are wrong, please validate against the DAI_ADD defn. It looks like we are also missing some macro defs for Time domain, these can be added too in order to avoid ambiguous definitions.

dnl DAI_ADD(pipeline,
dnl     pipe id, dai type, dai_index, dai_be,
dnl     buffer, periods, format,
dnl     period , priority, core, time_domain)
define(`DAI_ADD',
`undefine(`PIPELINE_ID')'
`undefine(`DAI_TYPE')'
`undefine(`DAI_INDEX')'
`undefine(`DAI_BE')'
`undefine(`DAI_BUF')'
`undefine(`DAI_PERIODS')'
`undefine(`DAI_FORMAT')'
`undefine(`SCHEDULE_PERIOD')'
`undefine(`SCHEDULE_PRIORITY')'
`undefine(`SCHEDULE_CORE')'
`undefine(`SCHEDULE_TIME_DOMAIN')'
`define(`PIPELINE_ID', $2)'
`define(`DAI_TYPE', STR($3))'
`define(`DAI_INDEX', STR($4))'
`define(`DAI_BE', $5)'
`define(`DAI_BUF', $6)'
`define(`DAI_NAME', $3$4)'
`define(`DAI_PERIODS', $7)'
`define(`DAI_FORMAT', $8)'
`define(`SCHEDULE_PERIOD', $9)'
`define(`SCHEDULE_PRIORITY', $10)'
`define(`SCHEDULE_CORE', $11)'
`define(`SCHEDULE_TIME_DOMAIN', $12)'
`include($1)'
`DEBUG_DAI($3, $4)'

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@lgirdwood Pierre's questions was should this be TIMER or DMA...? And I guess it is TIMER as I see only that defined anywhere. And then I see DAI_ADD macros without either TIMER or DMA that compiles to "" in conf files, which is alsp probably not good.... So should those then be DMA?

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and forget last comment about not using, was not grepping for tokens... so question is should the empty "" be DOMAIN_DMA?

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So in below topologies the TIME_DOMAIN is not specified so it is "":

sof-cht-max98090.m4
sof-cht-nocodec.m4
sof-cht-rt5682.m4
sof-imx8qxp-nocodec.m4
sof-imx8qxp-nocodec-sai.m4
sof-imx8qxp-cs42888.m4
sof-imx8qxp-wm8960.m4
sof-hsw-rt5640.m4
sof-bdw-codec.m4
sof-cht-src-50khz-pcm512x.m4
platform/intel/intel-generic-dmic.m4
sof-byt-codec.m4

Any objections I just change it to TIMER in all?

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@juimonen The imx8qxp ones are 100% DMA-driven, so TIMER might/will break them. No words on the other ones though.

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@juimonen all topologies use the SOC clock master so there's no problem using the TIMER
the two cases where the codec is master is wm8804 and some versions of pcm512x, those would need to remain DMA based.

In general when the DAI uses 'codec_slave' we can use the TIMER.

sof-apl-wm8804.m4:              SSP_CLOCK(bclk, 3072000, codec_master),
sof-apl-wm8804.m4:              SSP_CLOCK(fsync, 48000, codec_master),
sof-imx8qxp-wm8960.m4:          SAI_CLOCK(bclk, 3072000, codec_master),
sof-imx8qxp-wm8960.m4:          SAI_CLOCK(fsync, 48000, codec_master),

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@tlauda any comment here ?

1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)

# capture DAI is DMIC 1 using 2 periods
# Buffers use s32le format, with 16 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
DMIC_PIPELINE_16k_ID, DMIC, 1, dmic16k,
concat(`PIPELINE_SINK_', DMIC_PIPELINE_16k_ID), 2, s32le,
1000, 0, 0, 16000, 16000, 16000)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)

dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture)
dnl PCM_CAPTURE_ADD(name, pipeline, capture)
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32 changes: 17 additions & 15 deletions tools/topology/sof-bdw-codec.m4
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Expand Up @@ -45,12 +45,27 @@ PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,
1000, 0, 0,
48000, 48000, 48000)

#
# DAI configuration
#
# SSP port 0 is our only pipeline DAI
#

# playback DAI is SSP0 using 2 periods
# Buffers use s24le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, 0, Codec,
PIPELINE_SOURCE_1, 2, s24le,
1000, 1, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le.
# 2000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4,
3, 1, 2, s32le,
2000, 0, 0,
8000, 96000, 48000)
8000, 96000, 48000,
SCHEDULE_TIME_DOMAIN_DMA,
PIPELINE_PLAYBACK_SCHED_COMP_1)
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leave broadwell with DMA


# Connect pipelines together
SectionGraph."PIPE_NAME" {
Expand All @@ -62,25 +77,12 @@ SectionGraph."PIPE_NAME" {
]
}

#
# DAI configuration
#
# SSP port 0 is our only pipeline DAI
#

# playback DAI is SSP0 using 2 periods
# Buffers use s24le format, 1000us deadline on core 0 with priority 1
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, 0, Codec,
PIPELINE_SOURCE_1, 2, s24le,
1000, 1, 0)

# capture DAI is SSP0 using 2 periods
# Buffers use s24le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
2, SSP, 0, Codec,
PIPELINE_SINK_2, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Low Latency
PCM_DUPLEX_ADD(Low Latency, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
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7 changes: 4 additions & 3 deletions tools/topology/sof-byt-codec.m4
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Expand Up @@ -62,15 +62,16 @@ PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, 2, SSP2-Codec,
PIPELINE_SOURCE_1, 2, s24le,
1000, 1, 0)
1000, 1, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le.
# 4000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4,
3, 1, 2, s16le,
4000, 0, 0,
8000, 96000, 48000,
0, PIPELINE_PLAYBACK_SCHED_COMP_1)
SCHEDULE_TIME_DOMAIN_DMA,
PIPELINE_PLAYBACK_SCHED_COMP_1)

# Connect pipelines together
SectionGraph."PIPE_NAME" {
Expand All @@ -87,7 +88,7 @@ SectionGraph."PIPE_NAME" {
DAI_ADD(sof/pipe-dai-capture.m4,
2, SSP, 2, SSP2-Codec,
PIPELINE_SINK_2, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Low Latency
PCM_DUPLEX_ADD(Low Latency, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
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4 changes: 2 additions & 2 deletions tools/topology/sof-cht-max98090.m4
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Expand Up @@ -52,7 +52,7 @@ PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, 2, SSP2-Codec,
PIPELINE_SOURCE_1, 2, s16le,
1000, 1, 0)
1000, 1, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le.
# 4000us deadline on core 0 with priority 0
Expand All @@ -77,7 +77,7 @@ SectionGraph."pipe-cht-max98090" {
DAI_ADD(sof/pipe-dai-capture.m4,
2, SSP, 2, SSP2-Codec,
PIPELINE_SINK_2, 2, s16le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Low Latency
PCM_DUPLEX_ADD(Low Latency, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
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6 changes: 3 additions & 3 deletions tools/topology/sof-cht-nocodec.m4
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Expand Up @@ -56,15 +56,15 @@ PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, 2, NoCodec-2,
PIPELINE_SOURCE_1, 2, s24le,
1000, 1, 0)
1000, 1, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le.
# 4000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4,
3, 1, 2, s32le,
4000, 0, 0,
8000, 48000, 48000,
0, PIPELINE_PLAYBACK_SCHED_COMP_1)
SCHEDULE_TIME_DOMAIN_DMA, PIPELINE_PLAYBACK_SCHED_COMP_1)

# Connect pipelines together
SectionGraph."media-pipe" {
Expand All @@ -81,7 +81,7 @@ SectionGraph."media-pipe" {
DAI_ADD(sof/pipe-dai-capture.m4,
2, SSP, 2, NoCodec-2,
PIPELINE_SINK_2, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Low Latency
PCM_DUPLEX_ADD(Low Latency, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
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4 changes: 2 additions & 2 deletions tools/topology/sof-cht-rt5682.m4
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Expand Up @@ -48,14 +48,14 @@ PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, 2, SSP2-Codec,
PIPELINE_SOURCE_1, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

# capture DAI is SSP2 using 2 periods
# Buffers use s24le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
2, SSP, 2, SSP2-Codec,
PIPELINE_SINK_2, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Low Latency
PCM_DUPLEX_ADD(SSP2, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
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2 changes: 1 addition & 1 deletion tools/topology/sof-cht-src-50khz-pcm512x.m4
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Expand Up @@ -53,7 +53,7 @@ dnl deadline, priority, core)
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, 2, SSP2-Codec,
PIPELINE_SOURCE_1, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM, id 0
dnl PCM_PLAYBACK_ADD(name, pcm_id, playback)
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2 changes: 1 addition & 1 deletion tools/topology/sof-cml-rt5682.m4
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Expand Up @@ -159,7 +159,7 @@ DAI_ADD(sof/pipe-dai-playback.m4,
DAI_ADD(sof/pipe-dai-capture.m4,
8, DMIC, 1, dmic16k,
PIPELINE_SINK_8, 2, s32le,
16, 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)


# PCM Low Latency, id 0
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92 changes: 0 additions & 92 deletions tools/topology/sof-hsw-rt5640.m4
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2 changes: 1 addition & 1 deletion tools/topology/sof-imx8qxp-cs42888.m4
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Expand Up @@ -59,7 +59,7 @@ dnl period, priority, core, time_domain)
DAI_ADD(sof/pipe-dai-playback.m4,
1, ESAI, 0, ESAI0-Codec,
PIPELINE_SOURCE_1, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
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# capture DAI is ESAI0 using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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2 changes: 1 addition & 1 deletion tools/topology/sof-imx8qxp-nocodec-sai.m4
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Expand Up @@ -52,7 +52,7 @@ dnl deadline, priority, core)
DAI_ADD(sof/pipe-dai-playback.m4,
1, SAI, 1, NoCodec-0,
PIPELINE_SOURCE_1, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

dnl PCM_PLAYBACK_ADD(name, pcm_id, playback)

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2 changes: 1 addition & 1 deletion tools/topology/sof-imx8qxp-nocodec.m4
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Expand Up @@ -52,7 +52,7 @@ dnl deadline, priority, core)
DAI_ADD(sof/pipe-dai-playback.m4,
1, ESAI, 0, NoCodec-0,
PIPELINE_SOURCE_1, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

dnl PCM_PLAYBACK_ADD(name, pcm_id, playback)

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2 changes: 1 addition & 1 deletion tools/topology/sof-imx8qxp-wm8960.m4
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Expand Up @@ -58,7 +58,7 @@ dnl period, priority, core, time_domain)
DAI_ADD(sof/pipe-dai-playback.m4,
1, SAI, 1, be.wm8960-hifi,
PIPELINE_SOURCE_1, 2, s24le,
1000, 0, 0)
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)

# capture DAI is SAI1 using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
Expand Down